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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-03 23:50:40 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-03 23:50:40 +0000 |
| commit | 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 (patch) | |
| tree | 54a731f5142d082ed12dd47c2c4625ed0eb68619 /test | |
| parent | 762797d1af1b9308c79982aedd9bd2f585f46171 (diff) | |
| download | external_llvm-7ce057983ea7b8ad42d5cca1bb5d3f6941662269.zip external_llvm-7ce057983ea7b8ad42d5cca1bb5d3f6941662269.tar.gz external_llvm-7ce057983ea7b8ad42d5cca1bb5d3f6941662269.tar.bz2 | |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/arm_addrmode3.s | 8 | ||||
| -rw-r--r-- | test/MC/ARM/thumb2_instructions.s | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 7 |
3 files changed, 11 insertions, 6 deletions
diff --git a/test/MC/ARM/arm_addrmode3.s b/test/MC/ARM/arm_addrmode3.s index 0b9639e..e1dc020 100644 --- a/test/MC/ARM/arm_addrmode3.s +++ b/test/MC/ARM/arm_addrmode3.s @@ -1,12 +1,12 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s -@ CHECK: ldrsbt r1, [r0], +r2 @ encoding: [0xd2,0x10,0xb0,0xe0] +@ CHECK: ldrsbt r1, [r0], r2 @ encoding: [0xd2,0x10,0xb0,0xe0] @ CHECK: ldrsbt r1, [r0], #4 @ encoding: [0xd4,0x10,0xf0,0xe0] -@ CHECK: ldrsht r1, [r0], +r2 @ encoding: [0xf2,0x10,0xb0,0xe0] +@ CHECK: ldrsht r1, [r0], r2 @ encoding: [0xf2,0x10,0xb0,0xe0] @ CHECK: ldrsht r1, [r0], #4 @ encoding: [0xf4,0x10,0xf0,0xe0] -@ CHECK: ldrht r1, [r0], +r2 @ encoding: [0xb2,0x10,0xb0,0xe0] +@ CHECK: ldrht r1, [r0], r2 @ encoding: [0xb2,0x10,0xb0,0xe0] @ CHECK: ldrht r1, [r0], #4 @ encoding: [0xb4,0x10,0xf0,0xe0] -@ CHECK: strht r1, [r0], +r2 @ encoding: [0xb2,0x10,0xa0,0xe0] +@ CHECK: strht r1, [r0], r2 @ encoding: [0xb2,0x10,0xa0,0xe0] @ CHECK: strht r1, [r0], #4 @ encoding: [0xb4,0x10,0xe0,0xe0] ldrsbt r1, [r0], r2 ldrsbt r1, [r0], #4 diff --git a/test/MC/ARM/thumb2_instructions.s b/test/MC/ARM/thumb2_instructions.s index 71cd4ae..6bdf926 100644 --- a/test/MC/ARM/thumb2_instructions.s +++ b/test/MC/ARM/thumb2_instructions.s @@ -1,6 +1,8 @@ @ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding %s > %t @ RUN: FileCheck < %t %s +@ FIXME: This test is completely bogus. Replace it with real tests. +@ XFAIL: * .syntax unified .text diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index b15fa4f..24df6e1 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -45,8 +45,11 @@ # CHECK: isb 0x6f 0xf0 0x7f 0xf5 -# CHECK: ldclvc p5, cr15, [r8], #-0 -0x00 0xf5 0x78 0x7c +# FIXME: LDC encoding information is incorrect. Re-enable this along with more +# robust testing for other values when we get it fleshed out and working +# properly. +# CHECKx: ldclvc p5, cr15, [r8], #-0 +#0x00 0xf5 0x78 0x7c # CHECK: ldr r0, [r2], #15 0x0f 0x00 0x92 0xe4 |