This CL changes the function prologue and epilogue emitted on X86 when stack needs realignment.

It is intended to fix PR11468.

Old prologue and epilogue looked like this:
push %rbp
mov %rsp, %rbp
and $alignment, %rsp
push %r14
push %r15
...
pop %r15
pop %r14
mov %rbp, %rsp
pop %rbp

The problem was to reference the locations of callee-saved registers in exception handling:
locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would
take some effort to implement this in LLVM, as currently MachineLocation can only have the form
"Register + Offset". Funciton prologue and epilogue are now changed to:

push %rbp
mov %rsp, %rbp
push %14
push %15
and $alignment, %rsp
...
lea -$size_of_saved_registers(%rbp), %rsp
pop %r15
pop %r14
pop %rbp

Reviewed by Chad Rosier.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160248 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 48 insertions, 24 deletions

diff --git a/test/CodeGen/X86/dynamic-allocas-VLAs.ll b/test/CodeGen/X86/dynamic-allocas-VLAs.ll
index c7970d4..54ae39b 100644
--- a/test/CodeGen/X86/dynamic-allocas-VLAs.ll
+++ b/test/CodeGen/X86/dynamic-allocas-VLAs.ll
@@ -85,20 +85,19 @@ entry:
 ; CHECK: _t4
 ; CHECK: pushq %rbp
 ; CHECK: movq %rsp, %rbp
-; CHECK: andq $-32, %rsp
 ; CHECK: pushq %r14
 ; CHECK: pushq %rbx
-; CHECK: subq $[[STACKADJ:[0-9]+]], %rsp
+; CHECK: andq $-32, %rsp
+; CHECK: subq ${{[0-9]+}}, %rsp
 ; CHECK: movq %rsp, %rbx
 ;
 ; CHECK: leaq {{[0-9]*}}(%rbx), %rdi
 ; CHECK: leaq {{[0-9]*}}(%rbx), %rdx
 ; CHECK: callq   _t4_helper
 ;
-; CHECK: addq $[[STACKADJ]], %rsp
+; CHECK: leaq -16(%rbp), %rsp
 ; CHECK: popq %rbx
 ; CHECK: popq %r14
-; CHECK: movq %rbp, %rsp
 ; CHECK: popq %rbp
 }
 
@@ -176,19 +175,17 @@ entry:
 ; CHECK: _t7
 ; CHECK:     pushq %rbp
 ; CHECK:     movq %rsp, %rbp
-; CHECK:     andq $-32, %rsp
 ; CHECK:     pushq %rbx
-; CHECK:     subq $[[ADJ:[0-9]+]], %rsp
+; CHECK:     andq $-32, %rsp
+; CHECK:     subq ${{[0-9]+}}, %rsp
 ; CHECK:     movq %rsp, %rbx
 
 ; Stack adjustment for byval
 ; CHECK:     subq {{.*}}, %rsp
 ; CHECK:     callq _bar
 ; CHECK-NOT: addq {{.*}}, %rsp
-; CHECK:     movq %rbx, %rsp
-; CHECK:     addq $[[ADJ]], %rsp
+; CHECK:     leaq -8(%rbp), %rsp
 ; CHECK:     popq %rbx
-; CHECK:     movq %rbp, %rsp
 ; CHECK:     popq %rbp
 }
 
@@ -229,14 +226,12 @@ entry:
 ; FORCE-ALIGN: _t9
 ; FORCE-ALIGN: pushq %rbp
 ; FORCE-ALIGN: movq %rsp, %rbp
-; FORCE-ALIGN: andq $-32, %rsp
 ; FORCE-ALIGN: pushq %rbx
-; FORCE-ALIGN: subq $24, %rsp
+; FORCE-ALIGN: andq $-32, %rsp
+; FORCE-ALIGN: subq $32, %rsp
 ; FORCE-ALIGN: movq %rsp, %rbx
 
-; FORCE-ALIGN: movq %rbx, %rsp
-; FORCE-ALIGN: addq $24, %rsp
+; FORCE-ALIGN: leaq -8(%rbp), %rsp
 ; FORCE-ALIGN: popq %rbx
-; FORCE-ALIGN: movq %rbp, %rsp
 ; FORCE-ALIGN: popq %rbp
 }
diff --git a/test/CodeGen/X86/force-align-stack-alloca.ll b/test/CodeGen/X86/force-align-stack-alloca.ll
index ecef781..6d44559 100644
--- a/test/CodeGen/X86/force-align-stack-alloca.ll
+++ b/test/CodeGen/X86/force-align-stack-alloca.ll
@@ -19,10 +19,10 @@ define i64 @g(i32 %i) nounwind {
 ; CHECK: g:
 ; CHECK:      pushl  %ebp
 ; CHECK-NEXT: movl   %esp, %ebp
-; CHECK-NEXT: andl   $-32, %esp
 ; CHECK-NEXT: pushl
 ; CHECK-NEXT: pushl
-; CHECK-NEXT: subl   $24, %esp
+; CHECK-NEXT: andl   $-32, %esp
+; CHECK-NEXT: subl   $32, %esp
 ;
 ; Now setup the base pointer (%ebx).
 ; CHECK-NEXT: movl   %esp, %ebx
@@ -46,17 +46,13 @@ define i64 @g(i32 %i) nounwind {
 ; CHECK-NEXT: addl   $32, %esp
 ; CHECK-NOT:         {{[^ ,]*}}, %esp
 ;
-; Restore %esp from %ebx (base pointer) so we can pop the callee-saved
-; registers.  This is the state prior to the allocation of VLAs.
+; Restore %esp from %ebp (frame pointer) and subtract the size of
+; zone with callee-saved registers to pop them.
+; This is the state prior to stack realignment and the allocation of VLAs.
 ; CHECK-NOT:  popl
-; CHECK:      movl   %ebx, %esp
-; CHECK-NEXT: addl   $24, %esp
+; CHECK:      leal   -8(%ebp), %esp
 ; CHECK-NEXT: popl
 ; CHECK-NEXT: popl
-;
-; Finally we need to restore %esp from %ebp due to dynamic stack
-; realignment.
-; CHECK-NEXT: movl   %ebp, %esp
 ; CHECK-NEXT: popl   %ebp
 ; CHECK-NEXT: ret
 
diff --git a/test/CodeGen/X86/pr11468.ll b/test/CodeGen/X86/pr11468.ll
new file mode 100644
index 0000000..f7e9adb
--- /dev/null
+++ b/test/CodeGen/X86/pr11468.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -force-align-stack -stack-alignment=32 -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s
+; PR11468
+
+define void @f(i64 %sz) uwtable {
+entry:
+  %a = alloca i32, align 32
+  store volatile i32 0, i32* %a, align 32
+  ; force to push r14 on stack
+  call void asm sideeffect "nop", "~{r14},~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0
+  ret void
+
+; CHECK: _f
+; CHECK: pushq %rbp
+; CHECK: .cfi_offset %rbp, -16
+; CHECK: movq %rsp, %rbp
+; CHECK: .cfi_def_cfa_register %rbp
+
+; We first push register on stack, and then realign it, so that
+; .cfi_offset value is correct
+; CHECK: pushq %r14
+; CHECK: andq $-32, %rsp
+; CHECK: .cfi_offset %r14, -24
+
+; Restore %rsp from %rbp and subtract the total size of saved regsiters.
+; CHECK: leaq -8(%rbp), %rsp
+
+; Pop saved registers.
+; CHECK: popq %r14
+; CHECK: popq %rbp
+}
+
+!0 = metadata !{i32 125}
+