[mips] Print instructions "beq", "bne" and "or" using assembler pseudo

instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 35 insertions, 31 deletions

diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll
index 54268cd..0e60fe1 100644
--- a/test/CodeGen/Mips/atomic.ll
+++ b/test/CodeGen/Mips/atomic.ll
@@ -14,7 +14,7 @@ entry:
 ; CHECK-EL:   ll      $[[R1:[0-9]+]], 0($[[R0]])
 ; CHECK-EL:   addu    $[[R2:[0-9]+]], $[[R1]], $4
 ; CHECK-EL:   sc      $[[R2]], 0($[[R0]])
-; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R2]], $[[BB0]]
 
 ; CHECK-EB-LABEL:   AtomicLoadAdd32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
@@ -22,7 +22,7 @@ entry:
 ; CHECK-EB:   ll      $[[R1:[0-9]+]], 0($[[R0]])
 ; CHECK-EB:   addu    $[[R2:[0-9]+]], $[[R1]], $4
 ; CHECK-EB:   sc      $[[R2]], 0($[[R0]])
-; CHECK-EB:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R2]], $[[BB0]]
 }
 
 define i32 @AtomicLoadNand32(i32 %incr) nounwind {
@@ -37,7 +37,7 @@ entry:
 ; CHECK-EL:   and     $[[R3:[0-9]+]], $[[R1]], $4
 ; CHECK-EL:   nor     $[[R2:[0-9]+]], $zero, $[[R3]]
 ; CHECK-EL:   sc      $[[R2]], 0($[[R0]])
-; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R2]], $[[BB0]]
 
 ; CHECK-EB-LABEL:   AtomicLoadNand32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
@@ -46,7 +46,7 @@ entry:
 ; CHECK-EB:   and     $[[R3:[0-9]+]], $[[R1]], $4
 ; CHECK-EB:   nor     $[[R2:[0-9]+]], $zero, $[[R3]]
 ; CHECK-EB:   sc      $[[R2]], 0($[[R0]])
-; CHECK-EB:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R2]], $[[BB0]]
 }
 
 define i32 @AtomicSwap32(i32 %newval) nounwind {
@@ -62,14 +62,14 @@ entry:
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      ${{[0-9]+}}, 0($[[R0]])
 ; CHECK-EL:   sc      $[[R2:[0-9]+]], 0($[[R0]])
-; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R2]], $[[BB0]]
 
 ; CHECK-EB-LABEL:   AtomicSwap32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      ${{[0-9]+}}, 0($[[R0]])
 ; CHECK-EB:   sc      $[[R2:[0-9]+]], 0($[[R0]])
-; CHECK-EB:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R2]], $[[BB0]]
 }
 
 define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
@@ -86,7 +86,7 @@ entry:
 ; CHECK-EL:   ll      $2, 0($[[R0]])
 ; CHECK-EL:   bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
 ; CHECK-EL:   sc      $[[R2:[0-9]+]], 0($[[R0]])
-; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R2]], $[[BB0]]
 ; CHECK-EL:   $[[BB1]]:
 
 ; CHECK-EB-LABEL:   AtomicCmpSwap32:
@@ -95,7 +95,7 @@ entry:
 ; CHECK-EB:   ll      $2, 0($[[R0]])
 ; CHECK-EB:   bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
 ; CHECK-EB:   sc      $[[R2:[0-9]+]], 0($[[R0]])
-; CHECK-EB:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R2]], $[[BB0]]
 ; CHECK-EB:   $[[BB1]]:
 }
 
@@ -126,7 +126,7 @@ entry:
 ; CHECK-EL:   and     $[[R13:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EL:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EL:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EL:   and     $[[R15:[0-9]+]], $[[R10]], $[[R6]]
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R4]]
@@ -152,7 +152,7 @@ entry:
 ; CHECK-EB:   and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; CHECK-EB:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EB:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EB:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -183,7 +183,7 @@ entry:
 ; CHECK-EL:   and     $[[R13:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EL:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EL:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EL:   and     $[[R15:[0-9]+]], $[[R10]], $[[R6]]
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R4]]
@@ -209,7 +209,7 @@ entry:
 ; CHECK-EB:   and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; CHECK-EB:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EB:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EB:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -241,7 +241,7 @@ entry:
 ; CHECK-EL:   and     $[[R13:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EL:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EL:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EL:   and     $[[R15:[0-9]+]], $[[R10]], $[[R6]]
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R4]]
@@ -268,7 +268,7 @@ entry:
 ; CHECK-EB:   and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; CHECK-EB:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EB:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EB:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -298,7 +298,7 @@ entry:
 ; CHECK-EL:   and     $[[R13:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EL:   or      $[[R14:[0-9]+]], $[[R13]], $[[R18]]
 ; CHECK-EL:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EL:   and     $[[R15:[0-9]+]], $[[R10]], $[[R6]]
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R4]]
@@ -323,7 +323,7 @@ entry:
 ; CHECK-EB:   and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; CHECK-EB:   or      $[[R14:[0-9]+]], $[[R13]], $[[R18]]
 ; CHECK-EB:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EB:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -358,7 +358,7 @@ entry:
 ; CHECK-EL:   and     $[[R14:[0-9]+]], $[[R12]], $[[R7]]
 ; CHECK-EL:   or      $[[R15:[0-9]+]], $[[R14]], $[[R11]]
 ; CHECK-EL:   sc      $[[R15]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R15]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R15]], $[[BB0]]
 
 ; CHECK-EL:   $[[BB1]]:
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R13]], $[[R4]]
@@ -388,7 +388,7 @@ entry:
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
 ; CHECK-EB:   or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
 ; CHECK-EB:   sc      $[[R16]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R16]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R16]], $[[BB0]]
 
 ; CHECK-EB:   $[[BB1]]:
 ; CHECK-EB:   srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll
index 82e4730..869ecd9 100644
--- a/test/CodeGen/Mips/brdelayslot.ll
+++ b/test/CodeGen/Mips/brdelayslot.ll
@@ -133,7 +133,7 @@ declare void @foo11()
 ; SUCCBB-LABEL:      succbbs_loop1:
 ; SUCCBB:      blez $5, $BB
 ; SUCCBB-NEXT: addiu
-; SUCCBB:      bne ${{[0-9]+}}, $zero, $BB
+; SUCCBB:      bnez ${{[0-9]+}}, $BB
 ; SUCCBB-NEXT: addiu
 
 define i32 @succbbs_loop1(i32* nocapture %a, i32 %n) {
@@ -159,7 +159,7 @@ for.end:                                          ; preds = %for.body, %entry
 ; Check that the first branch has its slot filled.
 ;
 ; SUCCBB-LABEL:      succbbs_br1:
-; SUCCBB:      beq ${{[0-9]+}}, $zero, $BB
+; SUCCBB:      beqz ${{[0-9]+}}, $BB
 ; SUCCBB-NEXT: lw $25, %call16(foo100)
 
 define void @succbbs_br1(i32 %a) {
diff --git a/test/CodeGen/Mips/setcc-se.ll b/test/CodeGen/Mips/setcc-se.ll
index 50ee860..99071c4 100644
--- a/test/CodeGen/Mips/setcc-se.ll
+++ b/test/CodeGen/Mips/setcc-se.ll
@@ -24,7 +24,7 @@ entry:
 
 ; CHECK-LABEL: slti_beq0:
 ; CHECK: slti $[[R0:[0-9]+]], $4, -32768
-; CHECK: beq $[[R0]], $zero
+; CHECK: beqz $[[R0]]
 
 define void @slti_beq0(i32 %a) {
 entry:
@@ -57,7 +57,7 @@ if.end:
 
 ; CHECK-LABEL: slti_beq2:
 ; CHECK: slti $[[R0:[0-9]+]], $4, 32767
-; CHECK: beq $[[R0]], $zero
+; CHECK: beqz $[[R0]]
 
 define void @slti_beq2(i32 %a) {
 entry:
@@ -90,7 +90,7 @@ if.end:
 
 ; CHECK-LABEL: sltiu_beq0:
 ; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
-; CHECK: beq $[[R0]], $zero
+; CHECK: beqz $[[R0]]
 
 define void @sltiu_beq0(i32 %a) {
 entry:
@@ -123,7 +123,7 @@ if.end:
 
 ; CHECK-LABEL: sltiu_beq2:
 ; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
-; CHECK: beq $[[R0]], $zero
+; CHECK: beqz $[[R0]]
 
 define void @sltiu_beq2(i32 %a) {
 entry:
diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt
index a0885a4..313f59b 100644
--- a/test/MC/Disassembler/Mips/mips32_le.txt
+++ b/test/MC/Disassembler/Mips/mips32_le.txt
@@ -260,6 +260,12 @@
 # CHECK: mov.s $f6, $f7
 0x86 0x39 0x00 0x46
 
+# CHECK: move $7, $8
+0x21,0x38,0x00,0x01
+
+# CHECK: move $3, $2
+0x25,0x18,0x40,0x00
+
 # CHECK: msub   $6,  $7
 0x04 0x00 0xc7 0x70
 
diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s
index b3dba86..eccc288 100644
--- a/test/MC/Mips/mips-alu-instructions.s
+++ b/test/MC/Mips/mips-alu-instructions.s
@@ -13,7 +13,6 @@
 # CHECK:  ins    $19, $9, 6, 7   # encoding: [0x84,0x61,0x33,0x7d]
 # CHECK:  nor    $9, $6, $7      # encoding: [0x27,0x48,0xc7,0x00]
 # CHECK:  or     $3, $3, $5      # encoding: [0x25,0x18,0x65,0x00]
-# CHECK:  or     $3, $2, $zero   # encoding: [0x25,0x18,0x40,0x00]
 # CHECK:  ori    $4, $5, 17767   # encoding: [0x67,0x45,0xa4,0x34]
 # CHECK:  ori    $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x34]
 # CHECK:  ori    $11, $11, 128   # encoding: [0x80,0x00,0x6b,0x35]
@@ -45,7 +44,6 @@
      ins    $19, $9, 6,7
      nor    $9,  $6, $7
      or     $3,  $3, $5
-     or     $3,  $2, $zero
      or     $4,  $5, 17767
      ori    $9,  $6, 17767
      ori    $11, 128
diff --git a/test/MC/Mips/mips-jump-instructions.s b/test/MC/Mips/mips-jump-instructions.s
index bfc052c..989826a 100644
--- a/test/MC/Mips/mips-jump-instructions.s
+++ b/test/MC/Mips/mips-jump-instructions.s
@@ -1,6 +1,6 @@
 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \
 # RUN: FileCheck -check-prefix=CHECK32  %s
-# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64r2 | \
+# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | \
 # RUN: FileCheck -check-prefix=CHECK64  %s
 
 # Check that the assembler can handle the documented syntax
@@ -28,9 +28,9 @@
 # CHECK32:   nop                    # encoding: [0x00,0x00,0x00,0x00]
 # CHECK32:   bal  1332              # encoding: [0x4d,0x01,0x11,0x04]
 # CHECK32:   nop                    # encoding: [0x00,0x00,0x00,0x00]
-# CHECK32:   bne  $11, $zero, 1332  # encoding: [0x4d,0x01,0x60,0x15]
+# CHECK32:   bnez $11, 1332         # encoding: [0x4d,0x01,0x60,0x15]
 # CHECK32:   nop                    # encoding: [0x00,0x00,0x00,0x00]
-# CHECK32:   beq  $11, $zero, 1332  # encoding: [0x4d,0x01,0x60,0x11]
+# CHECK32:   beqz $11, 1332         # encoding: [0x4d,0x01,0x60,0x11]
 # CHECK32:   nop                    # encoding: [0x00,0x00,0x00,0x00]
 
 # CHECK64:   b 1332                 # encoding: [0x4d,0x01,0x00,0x10]
@@ -53,9 +53,9 @@
 # CHECK64:   nop                    # encoding: [0x00,0x00,0x00,0x00]
 # CHECK64:   bal     1332           # encoding: [0x4d,0x01,0x11,0x04]
 # CHECK64:   nop                    # encoding: [0x00,0x00,0x00,0x00]
-# CHECK64:   bne  $11, $zero, 1332  # encoding: [0x4d,0x01,0x60,0x15]
+# CHECK64:   bnez $11, 1332         # encoding: [0x4d,0x01,0x60,0x15]
 # CHECK64:   nop                    # encoding: [0x00,0x00,0x00,0x00]
-# CHECK64:   beq  $11, $zero, 1332  # encoding: [0x4d,0x01,0x60,0x11]
+# CHECK64:   beqz $11, 1332         # encoding: [0x4d,0x01,0x60,0x11]
 # CHECK64:   nop                    # encoding: [0x00,0x00,0x00,0x00]
 
 .set noreorder