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| author | Craig Topper <craig.topper@gmail.com> | 2011-11-21 01:12:36 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2011-11-21 01:12:36 +0000 |
| commit | a124f949527e36efc05d2dbc999ddce43791b4ec (patch) | |
| tree | 13ac28efc3fb1a6389eea22216c45fed7805a2b6 /test | |
| parent | 7912ef97ffde3ab3334143ddfb4cafdf04e2ebfc (diff) | |
| download | external_llvm-a124f949527e36efc05d2dbc999ddce43791b4ec.zip external_llvm-a124f949527e36efc05d2dbc999ddce43791b4ec.tar.gz external_llvm-a124f949527e36efc05d2dbc999ddce43791b4ec.tar.bz2 | |
Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145022 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/avx-shift.ll | 24 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx2-shift.ll | 20 |
2 files changed, 44 insertions, 0 deletions
diff --git a/test/CodeGen/X86/avx-shift.ll b/test/CodeGen/X86/avx-shift.ll index a33423d..681747b 100644 --- a/test/CodeGen/X86/avx-shift.ll +++ b/test/CodeGen/X86/avx-shift.ll @@ -112,3 +112,27 @@ define <8 x i32> @vshift08(<8 x i32> %a) nounwind { ret <8 x i32> %bitop } +;;; Uses shifts for sign extension +; CHECK: _sext_v16i16 +; CHECK: vpsllw +; CHECK: vpsraw +; CHECK: vpsllw +; CHECK: vpsraw +; CHECK: vinsertf128 +define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind { + %b = trunc <16 x i16> %a to <16 x i8> + %c = sext <16 x i8> %b to <16 x i16> + ret <16 x i16> %c +} + +; CHECK: _sext_v8i32 +; CHECK: vpslld +; CHECK: vpsrad +; CHECK: vpslld +; CHECK: vpsrad +; CHECK: vinsertf128 +define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind { + %b = trunc <8 x i32> %a to <8 x i16> + %c = sext <8 x i16> %b to <8 x i32> + ret <8 x i32> %c +} diff --git a/test/CodeGen/X86/avx2-shift.ll b/test/CodeGen/X86/avx2-shift.ll index b9d1edc..b6cf54e 100644 --- a/test/CodeGen/X86/avx2-shift.ll +++ b/test/CodeGen/X86/avx2-shift.ll @@ -246,3 +246,23 @@ define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind { ; CHECK: vpsubb ; CHECK: ret } + +; CHECK: _sext_v16i16 +; CHECK: vpsllw +; CHECK: vpsraw +; CHECK-NOT: vinsertf128 +define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind { + %b = trunc <16 x i16> %a to <16 x i8> + %c = sext <16 x i8> %b to <16 x i16> + ret <16 x i16> %c +} + +; CHECK: _sext_v8i32 +; CHECK: vpslld +; CHECK: vpsrad +; CHECK-NOT: vinsertf128 +define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind { + %b = trunc <8 x i32> %a to <8 x i16> + %c = sext <8 x i16> %b to <8 x i32> + ret <8 x i32> %c +} |