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authorChris Lattner <sabre@nondot.org>2011-01-16 02:27:38 +0000
committerChris Lattner <sabre@nondot.org>2011-01-16 02:27:38 +0000
commitb99fdee325fe677081dc27bb7d719518452f3256 (patch)
tree1cc0d2b5c6b91e65403ff1baf828094df4bf016c /test
parentd5f656f48b98b4fc4dcb131f113316ba04180f11 (diff)
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reapply my fix for PR8961 with a tweak to properly handle
multi-instruction sequences like calls. Many thanks to Jakob for finding a testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123559 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/X86/fast-isel-gep.ll17
1 files changed, 17 insertions, 0 deletions
diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll
index 577dd72..622a1ff 100644
--- a/test/CodeGen/X86/fast-isel-gep.ll
+++ b/test/CodeGen/X86/fast-isel-gep.ll
@@ -70,3 +70,20 @@ entry:
; X64: test4:
; X64: 128(%r{{.*}},%r{{.*}},8)
}
+
+; PR8961 - Make sure the sext for the GEP addressing comes before the load that
+; is folded.
+define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind {
+ %v8 = getelementptr i8* %A, i32 %I
+ %v9 = bitcast i8* %v8 to i64*
+ %v10 = load i64* %v9
+ %v11 = add i64 %B, %v10
+ ret i64 %v11
+; X64: test5:
+; X64: movslq %esi, %rax
+; X64-NEXT: movq (%rdi,%rax), %rax
+; X64-NEXT: addq %rdx, %rax
+; X64-NEXT: ret
+}
+
+