ARM: allow predicated barriers in Thumb mode

The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 45 insertions, 10 deletions

diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll
index f1c097c..5e3a7d1 100644
--- a/test/CodeGen/Thumb2/thumb2-branch.ll
+++ b/test/CodeGen/Thumb2/thumb2-branch.ll
@@ -1,8 +1,10 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
-; If-conversion defeats the purpose of this test, which is to check conditional
-; branch generation, so use memory barrier instruction to make sure it doesn't
+; If-conversion defeats the purpose of this test, which is to check
+; conditional branch generation, so a call to make sure it doesn't
 ; happen and we get actual branches.
 
+declare void @foo()
+
 define i32 @f1(i32 %a, i32 %b, i32* %v) {
 entry:
 ; CHECK: f1:
@@ -11,12 +13,12 @@ entry:
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
 
@@ -28,12 +30,12 @@ entry:
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
 
@@ -45,12 +47,12 @@ entry:
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
 
@@ -62,11 +64,11 @@ entry:
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s
index 82d6ae3..21fda1c 100644
--- a/test/MC/ARM/diagnostics.s
+++ b/test/MC/ARM/diagnostics.s
@@ -379,3 +379,17 @@
 
         nop.n
 @ CHECK-ERRORS: error: instruction with .n (narrow) qualifier not allowed in arm mode
+
+	dmbeq #5
+	dsble #15
+	isblo #7
+@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
+
+	dmblt
+	dsbne
+	isbeq
+@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
diff --git a/test/MC/ARM/thumb-only-conditionals.s b/test/MC/ARM/thumb-only-conditionals.s
new file mode 100644
index 0000000..55b2cf4
--- /dev/null
+++ b/test/MC/ARM/thumb-only-conditionals.s
@@ -0,0 +1,19 @@
+@ RUN: llvm-mc -triple=thumbv7-apple-ios -o - %s | FileCheck %s
+
+        itte eq
+        dmbeq #11
+        dsbeq #7
+        isbne #15
+@ CHECK: itte eq
+@ CHECK-NEXT: dmbeq ish
+@ CHECK-NEXT: dsbeq nsh
+@ CHECK-NEXT: isbne sy
+
+        itet le
+        dmble
+        dsbgt
+        isble
+@ CHECK: itet le
+@ CHECK-NEXT: dmble sy
+@ CHECK-NEXT: dsbgt sy
+@ CHECK-NEXT: isble sy