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| author | Kevin Enderby <enderby@apple.com> | 2012-04-17 00:49:27 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2012-04-17 00:49:27 +0000 |
| commit | c5a2a33938182ccc5a1a94f7e1e2b3fdaff6a8b1 (patch) | |
| tree | 59977cb73560023597b41705cf55c6361c8dc7bb /test | |
| parent | 8975f510c0c69ff5a5f33fbb57f00b615a558368 (diff) | |
| download | external_llvm-c5a2a33938182ccc5a1a94f7e1e2b3fdaff6a8b1.zip external_llvm-c5a2a33938182ccc5a1a94f7e1e2b3fdaff6a8b1.tar.gz external_llvm-c5a2a33938182ccc5a1a94f7e1e2b3fdaff6a8b1.tar.bz2 | |
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/Disassembler/ARM/neon.txt | 37 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/neont2.txt | 38 |
2 files changed, 75 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index 58fe20e..c5dbee3 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -2243,3 +2243,40 @@ # CHECK: vld4.16 {d8, d10, d12, d14}, [r4] 0x8f 0x81 0x24 0xf4 # CHECK: vld4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11256967 +0x0f 0x0d 0xa2 0xf4 +# CHECK: vld2.8 {d0[], d1[]}, [r2] +0x4f 0x0d 0xa2 0xf4 +# CHECK: vld2.16 {d0[], d1[]}, [r2] +0x8f 0x0d 0xa2 0xf4 +# CHECK: vld2.32 {d0[], d1[]}, [r2] +0x0d 0x0d 0xa2 0xf4 +# CHECK: vld2.8 {d0[], d1[]}, [r2]! +0x4d 0x0d 0xa2 0xf4 +# CHECK: vld2.16 {d0[], d1[]}, [r2]! +0x8d 0x0d 0xa2 0xf4 +# CHECK: vld2.32 {d0[], d1[]}, [r2]! +0x03 0x0d 0xa2 0xf4 +# CHECK: vld2.8 {d0[], d1[]}, [r2], r3 +0x43 0x0d 0xa2 0xf4 +# CHECK: vld2.16 {d0[], d1[]}, [r2], r3 +0x83 0x0d 0xa2 0xf4 +# CHECK: vld2.32 {d0[], d1[]}, [r2], r3 +0x2f 0x0d 0xa3 0xf4 +# CHECK: vld2.8 {d0[], d2[]}, [r3] +0x6f 0x0d 0xa3 0xf4 +# CHECK: vld2.16 {d0[], d2[]}, [r3] +0xaf 0x0d 0xa3 0xf4 +# CHECK: vld2.32 {d0[], d2[]}, [r3] +0x2d 0x0d 0xa3 0xf4 +# CHECK: vld2.8 {d0[], d2[]}, [r3]! +0x6d 0x0d 0xa3 0xf4 +# CHECK: vld2.16 {d0[], d2[]}, [r3]! +0xad 0x0d 0xa3 0xf4 +# CHECK: vld2.32 {d0[], d2[]}, [r3]! +0x24 0x0d 0xa3 0xf4 +# CHECK: vld2.8 {d0[], d2[]}, [r3], r4 +0x64 0x0d 0xa3 0xf4 +0xa4 0x0d 0xa3 0xf4 +# CHECK: vld2.32 {d0[], d2[]}, [r3], r4 diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index efe7e60..65cd230 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1960,3 +1960,41 @@ # CHECK: vld4.16 {d8, d10, d12, d14}, [r4] 0x24 0xf9 0x8f 0x81 # CHECK: vld4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11256967 +0xa2 0xf9 0x0f 0x0d +# CHECK: vld2.8 {d0[], d1[]}, [r2] +0xa2 0xf9 0x4f 0x0d +# CHECK: vld2.16 {d0[], d1[]}, [r2] +0xa2 0xf9 0x8f 0x0d +# CHECK: vld2.32 {d0[], d1[]}, [r2] +0xa2 0xf9 0x0d 0x0d +# CHECK: vld2.8 {d0[], d1[]}, [r2]! +0xa2 0xf9 0x4d 0x0d +# CHECK: vld2.16 {d0[], d1[]}, [r2]! +0xa2 0xf9 0x8d 0x0d +# CHECK: vld2.32 {d0[], d1[]}, [r2]! +0xa2 0xf9 0x03 0x0d +# CHECK: vld2.8 {d0[], d1[]}, [r2], r3 +0xa2 0xf9 0x43 0x0d +# CHECK: vld2.16 {d0[], d1[]}, [r2], r3 +0xa2 0xf9 0x83 0x0d +# CHECK: vld2.32 {d0[], d1[]}, [r2], r3 +0xa3 0xf9 0x2f 0x0d +# CHECK: vld2.8 {d0[], d2[]}, [r3] +0xa3 0xf9 0x6f 0x0d +# CHECK: vld2.16 {d0[], d2[]}, [r3] +0xa3 0xf9 0xaf 0x0d +# CHECK: vld2.32 {d0[], d2[]}, [r3] +0xa3 0xf9 0x2d 0x0d +# CHECK: vld2.8 {d0[], d2[]}, [r3]! +0xa3 0xf9 0x6d 0x0d +# CHECK: vld2.16 {d0[], d2[]}, [r3]! +0xa3 0xf9 0xad 0x0d +# CHECK: vld2.32 {d0[], d2[]}, [r3]! +0xa3 0xf9 0x24 0x0d +# CHECK: vld2.8 {d0[], d2[]}, [r3], r4 +0xa3 0xf9 0x64 0x0d +# CHECK: vld2.16 {d0[], d2[]}, [r3], r4 +0xa3 0xf9 0xa4 0x0d +# CHECK: vld2.32 {d0[], d2[]}, [r3], r4 |