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author | Andrew Trick <atrick@apple.com> | 2013-08-30 04:27:29 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-08-30 04:27:29 +0000 |
commit | da6fc15f0fb26ebbe42ab96e0d066bbd5bdbb72e (patch) | |
tree | 90204955d891351885977e4682ad1d413a421117 /test | |
parent | 4c60b8a78d811a5b16ae45f6957933fb479bab58 (diff) | |
download | external_llvm-da6fc15f0fb26ebbe42ab96e0d066bbd5bdbb72e.zip external_llvm-da6fc15f0fb26ebbe42ab96e0d066bbd5bdbb72e.tar.gz external_llvm-da6fc15f0fb26ebbe42ab96e0d066bbd5bdbb72e.tar.bz2 |
mi-sched: improve the generic register pressure comparison.
Only compare pressure within the same set. When multiple sets are
affected, we prioritize the most constrained set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189641 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/X86/misched-balance.ll | 15 | ||||
-rw-r--r-- | test/CodeGen/X86/misched-matmul.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/X86/misched-matrix.ll | 14 |
3 files changed, 15 insertions, 17 deletions
diff --git a/test/CodeGen/X86/misched-balance.ll b/test/CodeGen/X86/misched-balance.ll index 78c56d2..3d67023 100644 --- a/test/CodeGen/X86/misched-balance.ll +++ b/test/CodeGen/X86/misched-balance.ll @@ -1,5 +1,4 @@ -; RUN-disabled: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-machineinstrs | FileCheck %s -; RUN: true +; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-machineinstrs | FileCheck %s ; ; Verify that misched resource/latency balancy heuristics are sane. @@ -16,7 +15,7 @@ entry: ; Since mmult1 IR is already in good order, this effectively ensure ; the scheduler maintains source order. ; -; CHECK: %for.body +; CHECK-LABEL: %for.body ; CHECK-NOT: %rsp ; CHECK: imull 4 ; CHECK-NOT: {{imull|rsp}} @@ -46,7 +45,7 @@ entry: ; CHECK-NOT: {{imull|rsp}} ; CHECK: addl ; CHECK-NOT: {{imull|rsp}} -; CHECK: %end +; CHECK-LABEL: %end for.body: %indvars.iv42.i = phi i64 [ %indvars.iv.next43.i, %for.body ], [ 0, %entry ] %tmp57 = load i32* %tmp56, align 4 @@ -121,7 +120,7 @@ end: ; Unlike the above loop, this IR starts out bad and must be ; rescheduled. ; -; CHECK: %for.body +; CHECK-LABEL: %for.body ; CHECK-NOT: %rsp ; CHECK: imull 4 ; CHECK-NOT: {{imull|rsp}} @@ -151,7 +150,7 @@ end: ; CHECK-NOT: {{imull|rsp}} ; CHECK: addl ; CHECK-NOT: {{imull|rsp}} -; CHECK: %end +; CHECK-LABEL: %end define void @unrolled_mmult2(i32* %tmp55, i32* %tmp56, i32* %pre, i32* %pre94, i32* %pre95, i32* %pre96, i32* %pre97, i32* %pre98, i32* %pre99, i32* %pre100, i32* %pre101, i32* %pre102, i32* %pre103, i32* %pre104) @@ -233,8 +232,8 @@ end: ; balanced heuristics are interesting here because we have resource, ; latency, and register limits all at once. For now, simply check that ; we don't use any callee-saves. -; CHECK: @encpc1 -; CHECK: %entry +; CHECK-LABEL: @encpc1 +; CHECK-LABEL: %entry ; CHECK-NOT: push ; CHECK-NOT: pop ; CHECK: ret diff --git a/test/CodeGen/X86/misched-matmul.ll b/test/CodeGen/X86/misched-matmul.ll index c13ac6a..fe78e70 100644 --- a/test/CodeGen/X86/misched-matmul.ll +++ b/test/CodeGen/X86/misched-matmul.ll @@ -1,6 +1,5 @@ ; REQUIRES: asserts -; RUN-disabled: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -stats 2>&1 | FileCheck %s -; RUN: true +; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -stats 2>&1 | FileCheck %s ; ; Verify that register pressure heuristics are working in MachineScheduler. ; diff --git a/test/CodeGen/X86/misched-matrix.ll b/test/CodeGen/X86/misched-matrix.ll index c602a0a..23b561f 100644 --- a/test/CodeGen/X86/misched-matrix.ll +++ b/test/CodeGen/X86/misched-matrix.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ ; RUN: -misched-topdown -verify-machineinstrs \ -; RUN: | FileCheck %s -check-prefix=TOPDOWN-disabled +; RUN: | FileCheck %s -check-prefix=TOPDOWN ; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ ; RUN: -misched=ilpmin -verify-machineinstrs \ ; RUN: | FileCheck %s -check-prefix=ILPMIN @@ -15,19 +15,19 @@ ; been reordered with the stores. This tests the scheduler's cheap ; alias analysis ability (that doesn't require any AliasAnalysis pass). ; -; TOPDOWN-disabled: %for.body +; TOPDOWN-LABEL: %for.body ; TOPDOWN: movl %{{.*}}, ( ; TOPDOWN: imull {{[0-9]*}}( ; TOPDOWN: movl %{{.*}}, 4( ; TOPDOWN: imull {{[0-9]*}}( ; TOPDOWN: movl %{{.*}}, 8( ; TOPDOWN: movl %{{.*}}, 12( -; TOPDOWN: %for.end +; TOPDOWN-LABEL: %for.end ; ; For -misched=ilpmin, verify that each expression subtree is ; scheduled independently, and that the imull/adds are interleaved. ; -; ILPMIN: %for.body +; ILPMIN-LABEL: %for.body ; ILPMIN: movl %{{.*}}, ( ; ILPMIN: imull ; ILPMIN: imull @@ -53,12 +53,12 @@ ; ILPMIN: imull ; ILPMIN: addl ; ILPMIN: movl %{{.*}}, 12( -; ILPMIN: %for.end +; ILPMIN-LABEL: %for.end ; ; For -misched=ilpmax, verify that each expression subtree is ; scheduled independently, and that the imull/adds are clustered. ; -; ILPMAX: %for.body +; ILPMAX-LABEL: %for.body ; ILPMAX: movl %{{.*}}, ( ; ILPMAX: imull ; ILPMAX: imull @@ -84,7 +84,7 @@ ; ILPMAX: addl ; ILPMAX: addl ; ILPMAX: movl %{{.*}}, 12( -; ILPMAX: %for.end +; ILPMAX-LABEL: %for.end define void @mmult([4 x i32]* noalias nocapture %m1, [4 x i32]* noalias nocapture %m2, [4 x i32]* noalias nocapture %m3) nounwind uwtable ssp { |