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author | Evan Cheng <evan.cheng@apple.com> | 2010-09-23 06:55:34 +0000 |
---|---|---|
committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-23 06:55:34 +0000 |
commit | dd3a41a6b35f24d57fd3aba9043bd5321cce0cdb (patch) | |
tree | 1e4f45201128bd530872c474dc800e6f8f8a04e5 /test | |
parent | 108c8724663354050dc09bb1262c3e4511adf82f (diff) | |
download | external_llvm-dd3a41a6b35f24d57fd3aba9043bd5321cce0cdb.zip external_llvm-dd3a41a6b35f24d57fd3aba9043bd5321cce0cdb.tar.gz external_llvm-dd3a41a6b35f24d57fd3aba9043bd5321cce0cdb.tar.bz2 |
Disable codegen prepare critical edge splitting. Machine instruction passes now
break critical edges on demand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114633 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/ARM/lsr-on-unrolled-loops.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/Thumb/2010-07-15-debugOrdering.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/2008-02-18-TailMergingBug.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/lsr-reuse.ll | 5 | ||||
-rw-r--r-- | test/CodeGen/X86/phi-immediate-factoring.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/phys_subreg_coalesce-2.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/postra-licm.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/pr2659.ll | 7 | ||||
-rw-r--r-- | test/CodeGen/X86/tail-opts.ll | 15 | ||||
-rw-r--r-- | test/CodeGen/X86/tailcallfp2.ll | 4 |
10 files changed, 23 insertions, 24 deletions
diff --git a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll index 866be42..0a839e2 100644 --- a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll +++ b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll @@ -624,12 +624,12 @@ bb23: ; preds = %bb22, %bb20, %bb9, bb24: ; preds = %bb23 ; LSR should use count-down iteration to avoid requiring the trip count -; in a register, and it shouldn't require any reloads here. +; in a register. ; CHECK: @ %bb24 ; CHECK-NEXT: @ in Loop: Header=BB1_1 Depth=1 -; CHECK-NEXT: sub{{.*}} [[REGISTER:(r[0-9]+)|(lr)]], #1 -; CHECK-NEXT: bne.w +; CHECK: subs [[REGISTER:(r[0-9]+)|(lr)]], #1 +; CHECK: bne.w %92 = icmp eq i32 %tmp81, %indvar78 ; <i1> [#uses=1] %indvar.next79 = add i32 %indvar78, 1 ; <i32> [#uses=1] diff --git a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll index 9a6321b..06c0dfe 100644 --- a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll +++ b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll @@ -10,7 +10,7 @@ define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind { ; CHECK: blx ___muldf3 ; CHECK: blx ___muldf3 -; CHECK: beq LBB0_8 +; CHECK: beq LBB0_7 ; CHECK: blx ___muldf3 ; <label>:3 switch i32 %1, label %4 [ diff --git a/test/CodeGen/X86/2008-02-18-TailMergingBug.ll b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll index 7463a0e..bdacf50 100644 --- a/test/CodeGen/X86/2008-02-18-TailMergingBug.ll +++ b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& grep {Number of block tails merged} | grep 9 +; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& grep {Number of block tails merged} | grep 16 ; PR1909 @.str = internal constant [48 x i8] c"transformed bounds: (%.2f, %.2f), (%.2f, %.2f)\0A\00" ; <[48 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll index a740514..2a97629 100644 --- a/test/CodeGen/X86/lsr-reuse.ll +++ b/test/CodeGen/X86/lsr-reuse.ll @@ -389,7 +389,7 @@ return: ; rdar://7657764 ; CHECK: asd: -; CHECK: BB9_5: +; CHECK: BB9_4: ; CHECK-NEXT: addl (%r{{[^,]*}},%rdi,4), %e ; CHECK-NEXT: incq %rdi ; CHECK-NEXT: cmpq %rdi, %r{{[^,]*}} @@ -464,7 +464,7 @@ bb5: ; preds = %bb3, %entry ; And the one at %bb68, where we want to be sure to use superhero mode: -; CHECK: BB10_9: +; CHECK: BB10_7: ; CHECK-NEXT: movaps 48(%r{{[^,]*}}), %xmm{{.*}} ; CHECK-NEXT: mulps %xmm{{.*}}, %xmm{{.*}} ; CHECK-NEXT: movaps 32(%r{{[^,]*}}), %xmm{{.*}} @@ -484,7 +484,6 @@ bb5: ; preds = %bb3, %entry ; CHECK-NEXT: addq $64, %r{{.*}} ; CHECK-NEXT: addq $64, %r{{.*}} ; CHECK-NEXT: addq $-16, %r{{.*}} -; CHECK-NEXT: BB10_10: ; CHECK-NEXT: cmpq $15, %r{{.*}} ; CHECK-NEXT: jg diff --git a/test/CodeGen/X86/phi-immediate-factoring.ll b/test/CodeGen/X86/phi-immediate-factoring.ll index 8bed624..ef02af2 100644 --- a/test/CodeGen/X86/phi-immediate-factoring.ll +++ b/test/CodeGen/X86/phi-immediate-factoring.ll @@ -1,5 +1,5 @@ +; RUN: llc < %s -march=x86 -stats |& grep {Number of blocks eliminated} | grep 6 ; PR1296 -; RUN: llc < %s -march=x86 | grep {movl \$1} | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target triple = "i686-apple-darwin8" diff --git a/test/CodeGen/X86/phys_subreg_coalesce-2.ll b/test/CodeGen/X86/phys_subreg_coalesce-2.ll index 23c509c..13e804d 100644 --- a/test/CodeGen/X86/phys_subreg_coalesce-2.ll +++ b/test/CodeGen/X86/phys_subreg_coalesce-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep mov | count 5 +; RUN: llc < %s -march=x86 | grep mov | count 4 ; PR2659 define i32 @binomial(i32 %n, i32 %k) nounwind { diff --git a/test/CodeGen/X86/postra-licm.ll b/test/CodeGen/X86/postra-licm.ll index 97cc7b4..902c69b 100644 --- a/test/CodeGen/X86/postra-licm.ll +++ b/test/CodeGen/X86/postra-licm.ll @@ -68,7 +68,7 @@ bb26.preheader: ; preds = %imix_test.exit bb23: ; preds = %imix_test.exit unreachable -; X86-32: %bb26.preheader.bb28_crit_edge +; X86-32: %bb26.preheader ; X86-32: movl -16(%ebp), ; X86-32-NEXT: .align 4 ; X86-32-NEXT: %bb28 diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll index e5daf5d..54d043d 100644 --- a/test/CodeGen/X86/pr2659.ll +++ b/test/CodeGen/X86/pr2659.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5 +; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 4 ; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | FileCheck %s ; PR2659 @@ -14,10 +14,11 @@ forcond.preheader: ; preds = %entry %cmp44 = icmp eq i32 %k, 0 ; <i1> [#uses=1] br i1 %cmp44, label %afterfor, label %forbody -; CHECK: %forcond.preheader.forbody_crit_edge +; CHECK: %forcond.preheader ; CHECK: movl $1 ; CHECK-NOT: xorl -; CHECK-NEXT: movl +; CHECK-NOT: movl +; CHECK-NEXT: je ifthen: ; preds = %entry ret i32 0 diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll index 66e6f50..f546ac4 100644 --- a/test/CodeGen/X86/tail-opts.ll +++ b/test/CodeGen/X86/tail-opts.ll @@ -153,19 +153,16 @@ bb30: ; an unconditional jump to complete a two-way conditional branch. ; CHECK: c_expand_expr_stmt: -; CHECK: jmp .LBB3_7 -; CHECK-NEXT: .LBB3_12: +; CHECK: jmp .LBB3_11 +; CHECK-NEXT: .LBB3_9: ; CHECK-NEXT: movq 8(%rax), %rax +; CHECK-NEXT: xorb %dl, %dl ; CHECK-NEXT: movb 16(%rax), %al ; CHECK-NEXT: cmpb $16, %al -; CHECK-NEXT: je .LBB3_6 +; CHECK-NEXT: je .LBB3_11 ; CHECK-NEXT: cmpb $23, %al -; CHECK-NEXT: je .LBB3_6 -; CHECK-NEXT: jmp .LBB3_15 -; CHECK-NEXT: .LBB3_14: -; CHECK-NEXT: cmpb $23, %bl -; CHECK-NEXT: jne .LBB3_15 -; CHECK-NEXT: .LBB3_15: +; CHECK-NEXT: jne .LBB3_14 +; CHECK-NEXT: .LBB3_11: %0 = type { %struct.rtx_def* } %struct.lang_decl = type opaque diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll index 4ec127f..04c4e95 100644 --- a/test/CodeGen/X86/tailcallfp2.ll +++ b/test/CodeGen/X86/tailcallfp2.ll @@ -1,8 +1,9 @@ -; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%edx} +; RUN: llc < %s -march=x86 -tailcallopt | FileCheck %s declare i32 @putchar(i32) define fastcc i32 @checktail(i32 %x, i32* %f, i32 %g) nounwind { +; CHECK: checktail: %tmp1 = icmp sgt i32 %x, 0 br i1 %tmp1, label %if-then, label %if-else @@ -10,6 +11,7 @@ if-then: %fun_ptr = bitcast i32* %f to i32(i32, i32*, i32)* %arg1 = add i32 %x, -1 call i32 @putchar(i32 90) +; CHECK: jmpl *%e{{.*}} %res = tail call fastcc i32 %fun_ptr( i32 %arg1, i32 * %f, i32 %g) ret i32 %res |