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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-29 20:26:09 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-29 20:26:09 +0000 |
| commit | e1cf5902ec832cecdd5a94b9701930253d410741 (patch) | |
| tree | e052669ed3277aa0c729b28f73e9a04b9a105cad /test | |
| parent | c91d6263cf3c7d4f211f5b95c7b4dd822435c300 (diff) | |
| download | external_llvm-e1cf5902ec832cecdd5a94b9701930253d410741.zip external_llvm-e1cf5902ec832cecdd5a94b9701930253d410741.tar.gz external_llvm-e1cf5902ec832cecdd5a94b9701930253d410741.tar.bz2 | |
ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 49 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 6 |
2 files changed, 53 insertions, 2 deletions
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 1a27198..c99c435 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1732,8 +1732,53 @@ Lforward: @------------------------------------------------------------------------------ -@ FIXME: SRS -@------------------------------------------------------------------------------ +@ SRS +@------------------------------------------------------------------------------ + srsda sp, #5 + srsdb sp, #1 + srsia sp, #0 + srsib sp, #15 + + srsda sp!, #31 + srsdb sp!, #19 + srsia sp!, #2 + srsib sp!, #14 + + srsfa sp, #11 + srsea sp, #10 + srsfd sp, #9 + srsed sp, #5 + + srsfa sp!, #5 + srsea sp!, #5 + srsfd sp!, #5 + srsed sp!, #5 + + srs sp, #5 + srs sp!, #5 + +@ CHECK: srsda sp, #5 @ encoding: [0x05,0x05,0x4d,0xf8] +@ CHECK: srsdb sp, #1 @ encoding: [0x01,0x05,0x4d,0xf9] +@ CHECK: srsia sp, #0 @ encoding: [0x00,0x05,0xcd,0xf8] +@ CHECK: srsib sp, #15 @ encoding: [0x0f,0x05,0xcd,0xf9] + +@ CHECK: srsda sp!, #31 @ encoding: [0x1f,0x05,0x6d,0xf8] +@ CHECK: srsdb sp!, #19 @ encoding: [0x13,0x05,0x6d,0xf9] +@ CHECK: srsia sp!, #2 @ encoding: [0x02,0x05,0xed,0xf8] +@ CHECK: srsib sp!, #14 @ encoding: [0x0e,0x05,0xed,0xf9] + +@ CHECK: srsda sp, #11 @ encoding: [0x0b,0x05,0x4d,0xf8] +@ CHECK: srsdb sp, #10 @ encoding: [0x0a,0x05,0x4d,0xf9] +@ CHECK: srsia sp, #9 @ encoding: [0x09,0x05,0xcd,0xf8] +@ CHECK: srsib sp, #5 @ encoding: [0x05,0x05,0xcd,0xf9] + +@ CHECK: srsda sp!, #5 @ encoding: [0x05,0x05,0x6d,0xf8] +@ CHECK: srsdb sp!, #5 @ encoding: [0x05,0x05,0x6d,0xf9] +@ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8] +@ CHECK: srsib sp!, #5 @ encoding: [0x05,0x05,0xed,0xf9] + +@ CHECK: srsia sp, #5 @ encoding: [0x05,0x05,0xcd,0xf8] +@ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8] @------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 537ad55..b15fa4f 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -101,6 +101,12 @@ # CHECK: rfedb r0! 0x00 0x0a 0x30 0xf9 +# CHECK: srsdb sp!, #19 +0x13 0x05 0x6d 0xf9 + +# CHECK: srsia sp, #9 +0x09 0x05 0xcd 0xf8 + # CHECK-NOT: rsbeq r0, r2, r0, lsl #0 # CHECK: rsbeq r0, r2, r0 0x00 0x00 0x62 0x00 |