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authorJim Grosbach <grosbach@apple.com>2011-07-14 21:19:17 +0000
committerJim Grosbach <grosbach@apple.com>2011-07-14 21:19:17 +0000
commite540c7422ca13c950f0e8f6f93af7225bb7742a9 (patch)
tree7563224b6d63db11fe78575682435dbcf958bbf2 /test
parent5cf9fcdad197652f178b6038d7880e4f6c5f68b5 (diff)
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external_llvm-e540c7422ca13c950f0e8f6f93af7225bb7742a9.tar.gz
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ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/MC/ARM/arm_instructions.s4
-rw-r--r--test/MC/ARM/basic-arm-instructions.s18
-rw-r--r--test/MC/ARM/diagnostics.s10
3 files changed, 28 insertions, 4 deletions
diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s
index 7ae0166..091ba72 100644
--- a/test/MC/ARM/arm_instructions.s
+++ b/test/MC/ARM/arm_instructions.s
@@ -89,8 +89,6 @@
@ CHECK: mrs r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1]
mrs r8, cpsr
-@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee]
- mcr p7, #1, r5, c1, c1, #4
@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
mrc p14, #0, r1, c1, c2, #4
@ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xec]
@@ -98,8 +96,6 @@
@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec]
mrrc p7, #1, r5, r4, c1
-@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]
- mcr2 p7, #1, r5, c1, c1, #4
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
mrc2 p14, #0, r1, c1, c2, #4
@ CHECK: mcrr2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xfc]
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 130f0b4..8d04ac3 100644
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -619,6 +619,24 @@ _func:
@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8]
@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9]
+@------------------------------------------------------------------------------
+@ FIXME: LDR*
+@------------------------------------------------------------------------------
+@------------------------------------------------------------------------------
+@ FIXME: LSL
+@------------------------------------------------------------------------------
+@------------------------------------------------------------------------------
+@ FIXME: LSR
+@------------------------------------------------------------------------------
+
+@------------------------------------------------------------------------------
+@ MCR/MCR2
+@------------------------------------------------------------------------------
+ mcr p7, #1, r5, c1, c1, #4
+ mcr2 p7, #1, r5, c1, c1, #4
+
+@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee]
+@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]
@------------------------------------------------------------------------------
@ STM*
diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s
index a173cdb..f65df0f 100644
--- a/test/MC/ARM/diagnostics.s
+++ b/test/MC/ARM/diagnostics.s
@@ -68,3 +68,13 @@
@ CHECK-ERRORS: error: invalid operand for instruction
@ Double-check that we're synced up with the right diagnostics.
@ CHECK-ERRORS: dbg #16
+
+ @ Out of range immediate for MCR/MCR2
+ mcr p7, #8, r5, c1, c1, #4
+ mcr p7, #2, r5, c1, c1, #8
+ mcr2 p7, #8, r5, c1, c1, #4
+ mcr2 p7, #1, r5, c1, c1, #8
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction