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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-09-16 10:29:42 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-09-16 10:29:42 +0000 |
| commit | e925f7dbbf497412cd0cc3f67b9b96fed0cc3712 (patch) | |
| tree | d437b605c6c2a28eebc0587ab88f8342319ef300 /test | |
| parent | 9bc7603750926c15648dae0d31a5451861a0d11e (diff) | |
| download | external_llvm-e925f7dbbf497412cd0cc3f67b9b96fed0cc3712.zip external_llvm-e925f7dbbf497412cd0cc3f67b9b96fed0cc3712.tar.gz external_llvm-e925f7dbbf497412cd0cc3f67b9b96fed0cc3712.tar.bz2 | |
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/Mips/mips-fpu-instructions.s | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s index eb1f6be..be0a900 100644 --- a/test/MC/Mips/mips-fpu-instructions.s +++ b/test/MC/Mips/mips-fpu-instructions.s @@ -169,6 +169,10 @@ # CHECK: swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e] # CHECK: mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44] # CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44] +# CHECK: swc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xeb] +# CHECK: sdc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xfb] +# CHECK: lwc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xcb] +# CHECK: ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb] cfc1 $a2,$0 ctc1 $10,$31 @@ -200,3 +204,7 @@ swxc1 $f26, $s2($s6) mfhc1 $17, $f4 mthc1 $17, $f6 + swc2 $4, 16($sp) + sdc2 $4, 16($sp) + lwc2 $11, 12($ra) + ldc2 $11, 12($ra) |