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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-21 22:56:30 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-21 22:56:30 +0000 |
| commit | f790193aec11747bb35206d2c79e0c5ffbc6dc7f (patch) | |
| tree | 08307eeda7651a10919464f6494f9cd4dde58f4f /test | |
| parent | 86fdff0fa79b2c00cb68a2961cca0466eb50d666 (diff) | |
| download | external_llvm-f790193aec11747bb35206d2c79e0c5ffbc6dc7f.zip external_llvm-f790193aec11747bb35206d2c79e0c5ffbc6dc7f.tar.gz external_llvm-f790193aec11747bb35206d2c79e0c5ffbc6dc7f.tar.bz2 | |
ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/arm_instructions.s | 3 | ||||
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 52 |
2 files changed, 52 insertions, 3 deletions
diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index b702038..68558d8 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -57,9 +57,6 @@ @ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1] mvns r1,r2 -@ CHECK: rsc r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0] - rsc r1,r2,r3 - @ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7] bfi r0, r0, #5, #7 diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 71d3a13..cf41ee8 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1164,6 +1164,58 @@ _func: @ CHECK: rsb r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x66,0xe0] @ CHECK: rsb r4, r4, r5, rrx @ encoding: [0x65,0x40,0x64,0xe0] +@------------------------------------------------------------------------------ +@ RSC +@------------------------------------------------------------------------------ + rsc r4, r5, #0xf000 + rsc r4, r5, r6 + rsc r4, r5, r6, lsl #5 + rsclo r4, r5, r6, lsr #5 + rsc r4, r5, r6, lsr #5 + rsc r4, r5, r6, asr #5 + rsc r4, r5, r6, ror #5 + rsc r6, r7, r8, lsl r9 + rsc r6, r7, r8, lsr r9 + rsc r6, r7, r8, asr r9 + rscle r6, r7, r8, ror r9 + + @ destination register is optional + rsc r5, #0xf000 + rsc r4, r5 + rsc r4, r5, lsl #5 + rsc r4, r5, lsr #5 + rscne r4, r5, lsr #5 + rsc r4, r5, asr #5 + rsc r4, r5, ror #5 + rscgt r6, r7, lsl r9 + rsc r6, r7, lsr r9 + rsc r6, r7, asr r9 + rsc r6, r7, ror r9 + +@ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2] +@ CHECK: rsc r4, r5, r6 @ encoding: [0x06,0x40,0xe5,0xe0] +@ CHECK: rsc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xe5,0xe0] +@ CHECK: rsclo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xe5,0x30] +@ CHECK: rsc r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xe5,0xe0] +@ CHECK: rsc r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0xe5,0xe0] +@ CHECK: rsc r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0xe5,0xe0] +@ CHECK: rsc r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0xe7,0xe0] +@ CHECK: rsc r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0xe7,0xe0] +@ CHECK: rsc r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0xe7,0xe0] +@ CHECK: rscle r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xe7,0xd0] + +@ CHECK: rsc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xe5,0xe2] +@ CHECK: rsc r4, r4, r5 @ encoding: [0x05,0x40,0xe4,0xe0] +@ CHECK: rsc r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0xe4,0xe0] +@ CHECK: rsc r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xe4,0xe0] +@ CHECK: rscne r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xe4,0x10] +@ CHECK: rsc r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0xe4,0xe0] +@ CHECK: rsc r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0xe4,0xe0] +@ CHECK: rscgt r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0xe6,0xc0] +@ CHECK: rsc r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0xe6,0xe0] +@ CHECK: rsc r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0xe6,0xe0] +@ CHECK: rsc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xe6,0xe0] + @------------------------------------------------------------------------------ @ STM* |