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| author | Tim Northover <tnorthover@apple.com> | 2013-08-27 13:46:45 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-08-27 13:46:45 +0000 |
| commit | 5d8c2e460cac05dedf3466d630995f1475317fc9 (patch) | |
| tree | 9ab80c4f7be7f508466aef594c506b37ec2a6621 /unittests/IR | |
| parent | dcfa0f7a408e54f15f0237daf2336df852053c6b (diff) | |
| download | external_llvm-5d8c2e460cac05dedf3466d630995f1475317fc9.zip external_llvm-5d8c2e460cac05dedf3466d630995f1475317fc9.tar.gz external_llvm-5d8c2e460cac05dedf3466d630995f1475317fc9.tar.bz2 | |
DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap
We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N),
const), but this is only valid if the bits above 16 on the source pattern are
0, the checks we were doing on this were slightly wrong before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189348 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'unittests/IR')
0 files changed, 0 insertions, 0 deletions