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| author | Jim Grosbach <grosbach@apple.com> | 2012-07-17 00:47:06 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-07-17 00:47:06 +0000 |
| commit | ac915b48d8ba73a5d734be5c4a0e1d25cea93252 (patch) | |
| tree | 063d21fed58fe8b3515fc4f0b5bebcbc65f4d005 /utils/Misc | |
| parent | 1bda7863e37180d5c371bab58ceaab0bd8c290d1 (diff) | |
| download | external_llvm-ac915b48d8ba73a5d734be5c4a0e1d25cea93252.zip external_llvm-ac915b48d8ba73a5d734be5c4a0e1d25cea93252.tar.gz external_llvm-ac915b48d8ba73a5d734be5c4a0e1d25cea93252.tar.bz2 | |
TableGen: Allow conditional instruction pattern in multiclass.
Define a 'null_frag' SDPatternOperator node, which if referenced in an
instruction Pattern, results in the pattern being collapsed to be as-if
'[]' had been specified instead. This allows supporting a multiclass
definition where some instaniations have ISel patterns associated and
others do not.
For example,
multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> {
def _x : myI<(outs rc:), (ins rc:), []>;
def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>;
}
defm foo : myMulti<GRa, not>;
defm bar : myMulti<GRb>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/Misc')
0 files changed, 0 insertions, 0 deletions