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author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
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committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /utils/TableGen/CodeGenSchedule.h | |
parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'utils/TableGen/CodeGenSchedule.h')
-rw-r--r-- | utils/TableGen/CodeGenSchedule.h | 28 |
1 files changed, 25 insertions, 3 deletions
diff --git a/utils/TableGen/CodeGenSchedule.h b/utils/TableGen/CodeGenSchedule.h index 5ce679a..65ac602 100644 --- a/utils/TableGen/CodeGenSchedule.h +++ b/utils/TableGen/CodeGenSchedule.h @@ -56,7 +56,7 @@ struct CodeGenSchedRW { RecVec Aliases; CodeGenSchedRW() - : Index(0), TheDef(0), IsRead(false), IsAlias(false), + : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false), HasVariants(false), IsVariadic(false), IsSequence(false) {} CodeGenSchedRW(unsigned Idx, Record *Def) : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { @@ -74,7 +74,7 @@ struct CodeGenSchedRW { CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq, const std::string &Name) - : Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false), + : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) { assert(Sequence.size() > 1 && "implied sequence needs >1 RWs"); } @@ -142,7 +142,7 @@ struct CodeGenSchedClass { // off to join another inferred class. RecVec InstRWs; - CodeGenSchedClass(): Index(0), ItinClassDef(0) {} + CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {} bool isKeyEqual(Record *IC, const IdxVec &W, const IdxVec &R) { return ItinClassDef == IC && Writes == W && Reads == R; @@ -248,6 +248,28 @@ class CodeGenSchedModels { public: CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT); + // iterator access to the scheduling classes. + typedef std::vector<CodeGenSchedClass>::iterator class_iterator; + typedef std::vector<CodeGenSchedClass>::const_iterator const_class_iterator; + class_iterator classes_begin() { return SchedClasses.begin(); } + const_class_iterator classes_begin() const { return SchedClasses.begin(); } + class_iterator classes_end() { return SchedClasses.end(); } + const_class_iterator classes_end() const { return SchedClasses.end(); } + iterator_range<class_iterator> classes() { + return iterator_range<class_iterator>(classes_begin(), classes_end()); + } + iterator_range<const_class_iterator> classes() const { + return iterator_range<const_class_iterator>(classes_begin(), classes_end()); + } + iterator_range<class_iterator> explicit_classes() { + return iterator_range<class_iterator>( + classes_begin(), classes_begin() + NumInstrSchedClasses); + } + iterator_range<const_class_iterator> explicit_classes() const { + return iterator_range<const_class_iterator>( + classes_begin(), classes_begin() + NumInstrSchedClasses); + } + Record *getModelOrItinDef(Record *ProcDef) const { Record *ModelDef = ProcDef->getValueAsDef("SchedModel"); Record *ItinsDef = ProcDef->getValueAsDef("ProcItin"); |