add support for referencing registers and immediates,

building the tree to represent them but not emitting 
table entries for them yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96617 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 7 insertions, 2 deletions

diff --git a/utils/TableGen/DAGISelMatcherEmitter.cpp b/utils/TableGen/DAGISelMatcherEmitter.cpp
index 158fe7f..92b2a55 100644
--- a/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -125,8 +125,8 @@ EmitMatcher(const MatcherNode *N, unsigned Indent) {
        << *cast<EmitNodeMatcherNode>(N)->getPattern().getDstPattern() << "\n";
     OS.PadToColumn(Indent*2) << "OPC_Emit, /*XXX*/\n\n";
     return 1;
-  case MatcherNode::Record:
-    OS << "OPC_Record,";
+  case MatcherNode::RecordNode:
+    OS << "OPC_RecordNode,";
     OS.PadToColumn(CommentIndent) << "// "
        << cast<RecordMatcherNode>(N)->getWhatFor() << '\n';
     return 1;
@@ -212,6 +212,11 @@ EmitMatcher(const MatcherNode *N, unsigned Indent) {
     OS << "OPC_CheckChainCompatible, "
        << cast<CheckChainCompatibleMatcherNode>(N)->getPreviousOp() << ",\n";
     return 2;
+      
+  case MatcherNode::EmitInteger:
+  case MatcherNode::EmitRegister:
+      // FIXME: Implement.
+    return 0;
   }
   assert(0 && "Unreachable");
   return 0;