add emitter support for integer constants and simple physreg references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96663 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 14 insertions, 3 deletions

diff --git a/utils/TableGen/DAGISelMatcherEmitter.cpp b/utils/TableGen/DAGISelMatcherEmitter.cpp
index 92b2a55..4b16db3 100644
--- a/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -213,10 +213,21 @@ EmitMatcher(const MatcherNode *N, unsigned Indent) {
        << cast<CheckChainCompatibleMatcherNode>(N)->getPreviousOp() << ",\n";
     return 2;
       
-  case MatcherNode::EmitInteger:
+  case MatcherNode::EmitInteger: {
+    int64_t Val = cast<EmitIntegerMatcherNode>(N)->getValue();
+    OS << "OPC_EmitInteger" << ClassifyInt(Val) << ", "
+       << getEnumName(cast<EmitIntegerMatcherNode>(N)->getVT()) << ", ";
+    return EmitInt(Val, OS)+2;
+  }
+      
   case MatcherNode::EmitRegister:
-      // FIXME: Implement.
-    return 0;
+    OS << "OPC_EmitRegister, "
+       << getEnumName(cast<EmitRegisterMatcherNode>(N)->getVT()) << ", ";
+    if (Record *R = cast<EmitRegisterMatcherNode>(N)->getReg())
+      OS << getQualifiedName(R) << ",\n";
+    else
+      OS << "0 /*zero_reg*/,\n";
+    return 3;
   }
   assert(0 && "Unreachable");
   return 0;