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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-18 03:08:20 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-18 03:08:20 +0000 |
commit | 54c47c1ce94b9e549ef768e80fd004788d13ce85 (patch) | |
tree | 6e6092299320c03acddf968e617778dccca01e20 /utils/TableGen/RegisterInfoEmitter.cpp | |
parent | 4b2a174e21b7cfc2c45db895efc7c638e4c68538 (diff) | |
download | external_llvm-54c47c1ce94b9e549ef768e80fd004788d13ce85.zip external_llvm-54c47c1ce94b9e549ef768e80fd004788d13ce85.tar.gz external_llvm-54c47c1ce94b9e549ef768e80fd004788d13ce85.tar.bz2 |
Remove MethodProtos/MethodBodies and allocation_order_begin/end.
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.
The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.
It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/RegisterInfoEmitter.cpp')
-rw-r--r-- | utils/TableGen/RegisterInfoEmitter.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index bcdde34..dbde0db 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -117,7 +117,7 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { if (!RC.AltOrderSelect.empty()) OS << " ArrayRef<unsigned> " "getRawAllocationOrder(const MachineFunction&) const;\n"; - OS << RC.MethodProtos << " };\n"; + OS << " };\n"; // Output the extern for the instance. OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; @@ -356,7 +356,6 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Emit methods. for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { const CodeGenRegisterClass &RC = RegisterClasses[i]; - OS << RC.MethodBodies << "\n"; OS << RC.getName() << "Class::" << RC.getName() << "Class() : TargetRegisterClass(" << RC.getName() + "RegClassID" << ", " |