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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-12-19 16:53:28 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-12-19 16:53:28 +0000 |
| commit | a9f65b9a1f57dcf546399ac32bf89d71d20df5b9 (patch) | |
| tree | c285678a9d2c9dca31951b1c56318e60433b170f /utils/TableGen/SetTheory.h | |
| parent | 5b25cffdaed90512dcd858db5e71f37edc836c91 (diff) | |
| download | external_llvm-a9f65b9a1f57dcf546399ac32bf89d71d20df5b9.zip external_llvm-a9f65b9a1f57dcf546399ac32bf89d71d20df5b9.tar.gz external_llvm-a9f65b9a1f57dcf546399ac32bf89d71d20df5b9.tar.bz2 | |
Synthesize register classes for TRI::getMatchingSuperRegClass().
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results. The function is
still not auto-generated, so it still returns inexact results.
This produces these new register classes:
ARM:
QQPR_with_dsub_0_in_DPR_8
QQQQPR_with_dsub_0_in_DPR_8
X86:
GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
GR64_with_sub_16bit_in_GR16_NOREX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_with_sub_32bit_in_GR32_TC
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
GR64_with_sub_32bit_in_GR32_AD
GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX
The other targets in the tree are not weird enough to be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/SetTheory.h')
0 files changed, 0 insertions, 0 deletions