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authorStephen Hines <srhines@google.com>2015-04-01 18:49:24 +0000
committerGerrit Code Review <noreply-gerritcodereview@google.com>2015-04-01 18:49:26 +0000
commit3fa16bd6062e23bcdb82ed4dd965674792e6b761 (patch)
tree9348fc507292f7e8715d22d64ce5a32131b4f875 /utils/TableGen/X86DisassemblerTables.cpp
parentbeed47390a60f6f0c77532b3d3f76bb47ef49423 (diff)
parentebe69fe11e48d322045d5949c83283927a0d790b (diff)
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Merge "Update aosp/master LLVM for rebase to r230699."
Diffstat (limited to 'utils/TableGen/X86DisassemblerTables.cpp')
-rw-r--r--utils/TableGen/X86DisassemblerTables.cpp49
1 files changed, 31 insertions, 18 deletions
diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp
index d7e981c..fbe5502 100644
--- a/utils/TableGen/X86DisassemblerTables.cpp
+++ b/utils/TableGen/X86DisassemblerTables.cpp
@@ -75,13 +75,13 @@ static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
/// @return - True if child is a subset of parent, false otherwise.
static inline bool inheritsFrom(InstructionContext child,
InstructionContext parent,
- bool VEX_LIG = false) {
+ bool VEX_LIG = false, bool AdSize64 = false) {
if (child == parent)
return true;
switch (parent) {
case IC:
- return(inheritsFrom(child, IC_64BIT) ||
+ return(inheritsFrom(child, IC_64BIT, AdSize64) ||
inheritsFrom(child, IC_OPSIZE) ||
inheritsFrom(child, IC_ADSIZE) ||
inheritsFrom(child, IC_XD) ||
@@ -89,13 +89,19 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_64BIT:
return(inheritsFrom(child, IC_64BIT_REXW) ||
inheritsFrom(child, IC_64BIT_OPSIZE) ||
- inheritsFrom(child, IC_64BIT_ADSIZE) ||
+ (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) ||
inheritsFrom(child, IC_64BIT_XD) ||
inheritsFrom(child, IC_64BIT_XS));
case IC_OPSIZE:
- return inheritsFrom(child, IC_64BIT_OPSIZE);
+ return inheritsFrom(child, IC_64BIT_OPSIZE) ||
+ inheritsFrom(child, IC_OPSIZE_ADSIZE);
case IC_ADSIZE:
+ return inheritsFrom(child, IC_OPSIZE_ADSIZE);
+ case IC_OPSIZE_ADSIZE:
+ return false;
case IC_64BIT_ADSIZE:
+ return inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE);
+ case IC_64BIT_OPSIZE_ADSIZE:
return false;
case IC_XD:
return inheritsFrom(child, IC_64BIT_XD);
@@ -108,9 +114,12 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_64BIT_REXW:
return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
inheritsFrom(child, IC_64BIT_REXW_XD) ||
- inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
+ inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
+ (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)));
case IC_64BIT_OPSIZE:
- return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
+ return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
+ (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) ||
+ (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE));
case IC_64BIT_XD:
return(inheritsFrom(child, IC_64BIT_REXW_XD));
case IC_64BIT_XS:
@@ -121,6 +130,7 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_64BIT_REXW_XD:
case IC_64BIT_REXW_XS:
case IC_64BIT_REXW_OPSIZE:
+ case IC_64BIT_REXW_ADSIZE:
return false;
case IC_VEX:
return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
@@ -713,6 +723,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
(index & ATTR_OPSIZE))
o << "IC_64BIT_REXW_OPSIZE";
+ else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
+ (index & ATTR_ADSIZE))
+ o << "IC_64BIT_REXW_ADSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
o << "IC_64BIT_XD_OPSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
@@ -721,6 +734,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
o << "IC_64BIT_XS";
else if ((index & ATTR_64BIT) && (index & ATTR_XD))
o << "IC_64BIT_XD";
+ else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE) &&
+ (index & ATTR_ADSIZE))
+ o << "IC_64BIT_OPSIZE_ADSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
o << "IC_64BIT_OPSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
@@ -737,6 +753,8 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
o << "IC_XS";
else if (index & ATTR_XD)
o << "IC_XD";
+ else if ((index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
+ o << "IC_OPSIZE_ADSIZE";
else if (index & ATTR_OPSIZE)
o << "IC_OPSIZE";
else if (index & ATTR_ADSIZE)
@@ -822,15 +840,6 @@ void DisassemblerTables::setTableFields(ModRMDecision &decision,
InstructionSpecifier &previousInfo =
InstructionSpecifiers[decision.instructionIDs[index]];
- // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
- // presence of the AdSize prefix. However, the disassembler doesn't
- // care about that difference in the instruction definition; it
- // handles 16-bit vs. 32-bit addressing for itself based purely
- // on the 0x67 prefix and the CPU mode. So there's no need to
- // disambiguate between them; just let them conflict/coexist.
- if (previousInfo.name + "_16" == newInfo.name)
- continue;
-
if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
newInfo.name == "XCHG32ar" ||
newInfo.name == "XCHG32ar64" ||
@@ -862,15 +871,19 @@ void DisassemblerTables::setTableFields(OpcodeType type,
const ModRMFilter &filter,
InstrUID uid,
bool is32bit,
- bool ignoresVEX_L) {
+ bool ignoresVEX_L,
+ unsigned addressSize) {
ContextDecision &decision = *Tables[type];
for (unsigned index = 0; index < IC_max; ++index) {
- if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
+ if ((is32bit || addressSize == 16) &&
+ inheritsFrom((InstructionContext)index, IC_64BIT))
continue;
+ bool adSize64 = addressSize == 64;
if (inheritsFrom((InstructionContext)index,
- InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
+ InstructionSpecifiers[uid].insnContext, ignoresVEX_L,
+ adSize64))
setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],
filter,
uid,