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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-08 22:51:23 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-08 22:51:23 +0000 |
| commit | b5e6eed4be00564e022fea3f1bc684533fd38607 (patch) | |
| tree | bb4f1e4c609d5bf95ea1eaff57e9cf3d4a843ea8 /utils/TableGen/X86RecognizableInstr.cpp | |
| parent | 01958a76702eae10fa2ccf7e8df292ad55f4daca (diff) | |
| download | external_llvm-b5e6eed4be00564e022fea3f1bc684533fd38607.zip external_llvm-b5e6eed4be00564e022fea3f1bc684533fd38607.tar.gz external_llvm-b5e6eed4be00564e022fea3f1bc684533fd38607.tar.bz2 | |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/X86RecognizableInstr.cpp')
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index b7085ae..5fe2bfe 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -212,6 +212,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); + HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); @@ -532,7 +533,12 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { "Unexpected number of operands for MRMSrcRegFrm"); HANDLE_OPERAND(roRegister) HANDLE_OPERAND(rmRegister) - HANDLE_OPTIONAL(immediate) + + if (HasVEX_4VPrefix) + // FIXME: encoding of registers in AVX is in 1's complement form. + HANDLE_OPTIONAL(rmRegister) + else + HANDLE_OPTIONAL(immediate) break; case X86Local::MRMSrcMem: // Operand 1 is a register operand in the Reg/Opcode field. |