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authorJim Grosbach <grosbach@apple.com>2011-03-11 20:18:05 +0000
committerJim Grosbach <grosbach@apple.com>2011-03-11 20:18:05 +0000
commit1558df79b4b2b6558c6d107b62e4dab2564bd793 (patch)
treeda64b6891ca86b463fba96e3bd385b7d4c3be993 /utils/TableGen
parentf0112a224ffcb6df3044ebb601437ba8ce5b033c (diff)
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ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
as for VREV64d32 and VREV64q32, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
-rw-r--r--utils/TableGen/ARMDecoderEmitter.cpp7
1 files changed, 0 insertions, 7 deletions
diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp
index 915f905..dd8e3455 100644
--- a/utils/TableGen/ARMDecoderEmitter.cpp
+++ b/utils/TableGen/ARMDecoderEmitter.cpp
@@ -1654,13 +1654,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
Name == "VEXTq16" || Name == "VEXTq32" || Name == "VEXTqf")
return false;
- // Vector Reverse is similar to Vector Extract. There is no distinction
- // between data types, other than size.
- //
- // VREV64df is equivalent to VREV64d32.
- // VREV64qf is equivalent to VREV64q32.
- if (Name == "VREV64df" || Name == "VREV64qf") return false;
-
// VDUPLNfd is equivalent to VDUPLN32d.
// VDUPLNfq is equivalent to VDUPLN32q.
// VLD1df is equivalent to VLD1d32.