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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-29 18:47:24 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-29 18:47:24 +0000 |
| commit | 2c6363a62df95b74468d9a561bbcb9edddeb3507 (patch) | |
| tree | 64e1dafa4afce7a9ed628ab455eac1a215f5d5b0 /utils/TableGen | |
| parent | ea2429896a9f4cf3176bf69e83d107f214630ec1 (diff) | |
| download | external_llvm-2c6363a62df95b74468d9a561bbcb9edddeb3507.zip external_llvm-2c6363a62df95b74468d9a561bbcb9edddeb3507.tar.gz external_llvm-2c6363a62df95b74468d9a561bbcb9edddeb3507.tar.bz2 | |
ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
0 files changed, 0 insertions, 0 deletions