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author | Jim Grosbach <grosbach@apple.com> | 2011-03-11 02:19:02 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2011-03-11 02:19:02 +0000 |
commit | 4a6d735105ffac5f58499ef5a5de8713b458b233 (patch) | |
tree | ad4e2d200aea58d68c8bc43b33221dddff7a0d55 /utils/TableGen | |
parent | 109d6dbe50753f102566cd4895b69fd13f62efa4 (diff) | |
download | external_llvm-4a6d735105ffac5f58499ef5a5de8713b458b233.zip external_llvm-4a6d735105ffac5f58499ef5a5de8713b458b233.tar.gz external_llvm-4a6d735105ffac5f58499ef5a5de8713b458b233.tar.bz2 |
Teach TableGen to pre-calculate register enum values when creating the
CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.
rdar://9066491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127456 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
-rw-r--r-- | utils/TableGen/DAGISelEmitter.cpp | 6 | ||||
-rw-r--r-- | utils/TableGen/DAGISelMatcher.h | 9 | ||||
-rw-r--r-- | utils/TableGen/DAGISelMatcherEmitter.cpp | 39 | ||||
-rw-r--r-- | utils/TableGen/DAGISelMatcherGen.cpp | 15 |
4 files changed, 36 insertions, 33 deletions
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index dee8f77..d66ae96 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -148,12 +148,8 @@ void DAGISelEmitter::run(raw_ostream &OS) { Matcher *TheMatcher = new ScopeMatcher(&PatternMatchers[0], PatternMatchers.size()); - CodeGenTarget Target(Records); - const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); - bool useEmitRegister2 = Registers.size() > 255; - TheMatcher = OptimizeMatcher(TheMatcher, CGP); //Matcher->dump(); - EmitMatcherTable(TheMatcher, CGP, useEmitRegister2, OS); + EmitMatcherTable(TheMatcher, CGP, OS); delete TheMatcher; } diff --git a/utils/TableGen/DAGISelMatcher.h b/utils/TableGen/DAGISelMatcher.h index d17051c..8ffe412 100644 --- a/utils/TableGen/DAGISelMatcher.h +++ b/utils/TableGen/DAGISelMatcher.h @@ -17,6 +17,7 @@ #include "llvm/Support/Casting.h" namespace llvm { + struct CodeGenRegister; class CodeGenDAGPatterns; class Matcher; class PatternToMatch; @@ -29,7 +30,7 @@ Matcher *ConvertPatternToMatcher(const PatternToMatch &Pattern,unsigned Variant, const CodeGenDAGPatterns &CGP); Matcher *OptimizeMatcher(Matcher *Matcher, const CodeGenDAGPatterns &CGP); void EmitMatcherTable(const Matcher *Matcher, const CodeGenDAGPatterns &CGP, - bool useEmitRegister2, raw_ostream &OS); + raw_ostream &OS); /// Matcher - Base class for all the the DAG ISel Matcher representation @@ -816,13 +817,13 @@ private: class EmitRegisterMatcher : public Matcher { /// Reg - The def for the register that we're emitting. If this is null, then /// this is a reference to zero_reg. - Record *Reg; + const CodeGenRegister *Reg; MVT::SimpleValueType VT; public: - EmitRegisterMatcher(Record *reg, MVT::SimpleValueType vt) + EmitRegisterMatcher(const CodeGenRegister *reg, MVT::SimpleValueType vt) : Matcher(EmitRegister), Reg(reg), VT(vt) {} - Record *getReg() const { return Reg; } + const CodeGenRegister *getReg() const { return Reg; } MVT::SimpleValueType getVT() const { return VT; } static inline bool classof(const Matcher *N) { diff --git a/utils/TableGen/DAGISelMatcherEmitter.cpp b/utils/TableGen/DAGISelMatcherEmitter.cpp index 3a71ddb..0b69af4 100644 --- a/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -43,11 +43,9 @@ class MatcherTableEmitter { DenseMap<Record*, unsigned> NodeXFormMap; std::vector<Record*> NodeXForms; - bool useEmitRegister2; - public: - MatcherTableEmitter(const CodeGenDAGPatterns &cgp, bool _useEmitRegister2) - : CGP(cgp), useEmitRegister2(_useEmitRegister2) {} + MatcherTableEmitter(const CodeGenDAGPatterns &cgp) + : CGP(cgp) {} unsigned EmitMatcherList(const Matcher *N, unsigned Indent, unsigned StartIdx, formatted_raw_ostream &OS); @@ -431,25 +429,20 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, return 3; } - case Matcher::EmitRegister: - if (useEmitRegister2) { - OS << "OPC_EmitRegister2, " - << getEnumName(cast<EmitRegisterMatcher>(N)->getVT()) << ", "; - if (Record *R = cast<EmitRegisterMatcher>(N)->getReg()) - OS << "TARGET_VAL(" << getQualifiedName(R) << "),\n"; - else { - OS << "TARGET_VAL(0) "; - if (!OmitComments) - OS << "/*zero_reg*/"; - OS << ",\n"; - } + case Matcher::EmitRegister: { + const EmitRegisterMatcher *Matcher = cast<EmitRegisterMatcher>(N); + const CodeGenRegister *Reg = Matcher->getReg(); + // If the enum value of the register is larger than one byte can handle, + // use EmitRegister2. + if (Reg && Reg->EnumValue > 255) { + OS << "OPC_EmitRegister2, " << getEnumName(Matcher->getVT()) << ", "; + OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n"; return 4; } else { - OS << "OPC_EmitRegister, " - << getEnumName(cast<EmitRegisterMatcher>(N)->getVT()) << ", "; - if (Record *R = cast<EmitRegisterMatcher>(N)->getReg()) - OS << getQualifiedName(R) << ",\n"; - else { + OS << "OPC_EmitRegister, " << getEnumName(Matcher->getVT()) << ", "; + if (Reg) { + OS << getQualifiedName(Reg->TheDef) << ",\n"; + } else { OS << "0 "; if (!OmitComments) OS << "/*zero_reg*/"; @@ -457,6 +450,7 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, } return 3; } + } case Matcher::EmitConvertToTarget: OS << "OPC_EmitConvertToTarget, " @@ -800,14 +794,13 @@ void MatcherTableEmitter::EmitHistogram(const Matcher *M, void llvm::EmitMatcherTable(const Matcher *TheMatcher, const CodeGenDAGPatterns &CGP, - bool useEmitRegister2, raw_ostream &O) { formatted_raw_ostream OS(O); OS << "// The main instruction selector code.\n"; OS << "SDNode *SelectCode(SDNode *N) {\n"; - MatcherTableEmitter MatcherEmitter(CGP, useEmitRegister2); + MatcherTableEmitter MatcherEmitter(CGP); OS << " // Some target values are emitted as 2 bytes, TARGET_VAL handles\n"; OS << " // this.\n"; diff --git a/utils/TableGen/DAGISelMatcherGen.cpp b/utils/TableGen/DAGISelMatcherGen.cpp index 7c0bade..393ac69 100644 --- a/utils/TableGen/DAGISelMatcherGen.cpp +++ b/utils/TableGen/DAGISelMatcherGen.cpp @@ -9,7 +9,9 @@ #include "DAGISelMatcher.h" #include "CodeGenDAGPatterns.h" +#include "CodeGenRegisters.h" #include "Record.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" #include <utility> @@ -91,6 +93,10 @@ namespace { /// CurPredicate - As we emit matcher nodes, this points to the latest check /// which should have future checks stuck into its Next position. Matcher *CurPredicate; + + /// RegisterDefMap - A map of register record definitions to the + /// corresponding target CodeGenRegister entry. + DenseMap<const Record *, const CodeGenRegister *> RegisterDefMap; public: MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp); @@ -159,6 +165,12 @@ MatcherGen::MatcherGen(const PatternToMatch &pattern, // If there are types that are manifestly known, infer them. InferPossibleTypes(); + + // Populate the map from records to CodeGenRegister entries. + const CodeGenTarget &CGT = CGP.getTargetInfo(); + const std::vector<CodeGenRegister> &Registers = CGT.getRegisters(); + for (unsigned i = 0, e = Registers.size(); i != e; ++i) + RegisterDefMap[Registers[i].TheDef] = &Registers[i]; } /// InferPossibleTypes - As we emit the pattern, we end up generating type @@ -578,7 +590,8 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N, // If this is an explicit register reference, handle it. if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) { if (DI->getDef()->isSubClassOf("Register")) { - AddMatcher(new EmitRegisterMatcher(DI->getDef(), N->getType(0))); + AddMatcher(new EmitRegisterMatcher(RegisterDefMap[DI->getDef()], + N->getType(0))); ResultOps.push_back(NextRecordedOperandNo++); return; } |