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author | Evan Cheng <evan.cheng@apple.com> | 2007-07-19 01:14:50 +0000 |
---|---|---|
committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-19 01:14:50 +0000 |
commit | 64d80e3387f328d21cd9cc06464b5de7861e3f27 (patch) | |
tree | 203a9dfb41eba2fd8bd65a1e8bb80f73e36c0771 /utils/TableGen | |
parent | 4558b807a2076e199bcb019f5edc9eabbc5922c1 (diff) | |
download | external_llvm-64d80e3387f328d21cd9cc06464b5de7861e3f27.zip external_llvm-64d80e3387f328d21cd9cc06464b5de7861e3f27.tar.gz external_llvm-64d80e3387f328d21cd9cc06464b5de7861e3f27.tar.bz2 |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
-rw-r--r-- | utils/TableGen/CodeGenInstruction.h | 4 | ||||
-rw-r--r-- | utils/TableGen/CodeGenTarget.cpp | 14 | ||||
-rw-r--r-- | utils/TableGen/DAGISelEmitter.cpp | 7 | ||||
-rw-r--r-- | utils/TableGen/Record.cpp | 14 |
4 files changed, 35 insertions, 4 deletions
diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h index 3f59c23..99da8d6 100644 --- a/utils/TableGen/CodeGenInstruction.h +++ b/utils/TableGen/CodeGenInstruction.h @@ -76,6 +76,10 @@ namespace llvm { MINumOperands(MINO), MIOperandInfo(MIOI) {} }; + /// NumDefs - Number of def operands declared. + /// + unsigned NumDefs; + /// OperandList - The list of declared operands, along with their declared /// type (which is a record). std::vector<OperandInfo> OperandList; diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index 2aabe51..268711d 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -376,13 +376,25 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) DagInit *DI; try { - DI = R->getValueAsDag("OperandList"); + DI = R->getValueAsDag("OutOperandList"); } catch (...) { // Error getting operand list, just ignore it (sparcv9). AsmString.clear(); OperandList.clear(); return; } + NumDefs = DI->getNumArgs(); + + DagInit *IDI; + try { + IDI = R->getValueAsDag("InOperandList"); + } catch (...) { + // Error getting operand list, just ignore it (sparcv9). + AsmString.clear(); + OperandList.clear(); + return; + } + DI = (DagInit*)(new BinOpInit(BinOpInit::CONCAT, DI, IDI))->Fold(); unsigned MIOperandNo = 0; std::set<std::string> OperandNames; diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index fcad318..e8049d6 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -1171,7 +1171,12 @@ void DAGISelEmitter::ParsePatternFragments(std::ostream &OS) { // Parse the operands list. DagInit *OpsList = Fragments[i]->getValueAsDag("Operands"); DefInit *OpsOp = dynamic_cast<DefInit*>(OpsList->getOperator()); - if (!OpsOp || OpsOp->getDef()->getName() != "ops") + // Special cases: ops == outs == ins. Different names are used to + // improve readibility. + if (!OpsOp || + (OpsOp->getDef()->getName() != "ops" && + OpsOp->getDef()->getName() != "outs" && + OpsOp->getDef()->getName() != "ins")) P->error("Operands list should start with '(ops ... '!"); // Copy over the arguments. diff --git a/utils/TableGen/Record.cpp b/utils/TableGen/Record.cpp index e81a361..75583bb 100644 --- a/utils/TableGen/Record.cpp +++ b/utils/TableGen/Record.cpp @@ -396,8 +396,18 @@ Init *BinOpInit::Fold() { if (LHSs && RHSs) { DefInit *LOp = dynamic_cast<DefInit*>(LHSs->getOperator()); DefInit *ROp = dynamic_cast<DefInit*>(RHSs->getOperator()); - if (LOp->getDef() != ROp->getDef()) - throw "Concated Dag operators do not match!"; + if (LOp->getDef() != ROp->getDef()) { + bool LIsOps = + LOp->getDef()->getName() == "outs" || + LOp->getDef()->getName() != "ins" || + LOp->getDef()->getName() != "defs"; + bool RIsOps = + ROp->getDef()->getName() == "outs" || + ROp->getDef()->getName() != "ins" || + ROp->getDef()->getName() != "defs"; + if (!LIsOps || !RIsOps) + throw "Concated Dag operators do not match!"; + } std::vector<Init*> Args; std::vector<std::string> ArgNames; for (unsigned i = 0, e = LHSs->getNumArgs(); i != e; ++i) { |