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authorTim Northover <Tim.Northover@arm.com>2013-01-09 13:32:04 +0000
committerTim Northover <Tim.Northover@arm.com>2013-01-09 13:32:04 +0000
commit7bf2e1b9ef797fda5de53956a1d2aea900ce794f (patch)
tree73af6ba21aaa381c4ea46502724745eff786d976 /utils/TableGen
parent2c8cf4b404e549482f593f62f9e27e0bab4a8b3f (diff)
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Check whether MCInst operand isImm before calling getImm.
When processing possible aliases, TableGen assumes that if an operand *can* be an immediate, then it always *will* be. This is incorrect for the AArch64 backend. This patch inserts a check in the generated code to make sure isImm is true first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171972 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
-rw-r--r--utils/TableGen/AsmWriterEmitter.cpp14
1 files changed, 10 insertions, 4 deletions
diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp
index a4114d9..73b083b 100644
--- a/utils/TableGen/AsmWriterEmitter.cpp
+++ b/utils/TableGen/AsmWriterEmitter.cpp
@@ -863,12 +863,18 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
break;
}
- case CodeGenInstAlias::ResultOperand::K_Imm:
- Cond = std::string("MI->getOperand(") +
- llvm::utostr(i) + ").getImm() == " +
- llvm::utostr(CGA->ResultOperands[i].getImm());
+ case CodeGenInstAlias::ResultOperand::K_Imm: {
+ std::string Op = "MI->getOperand(" + llvm::utostr(i) + ")";
+
+ // Just because the alias has an immediate result, doesn't mean the
+ // MCInst will. An MCExpr could be present, for example.
+ IAP->addCond(Op + ".isImm()");
+
+ Cond = Op + ".getImm() == "
+ + llvm::utostr(CGA->ResultOperands[i].getImm());
IAP->addCond(Cond);
break;
+ }
case CodeGenInstAlias::ResultOperand::K_Reg:
// If this is zero_reg, something's playing tricks we're not
// equipped to handle.