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authorJim Grosbach <grosbach@apple.com>2011-03-11 20:44:08 +0000
committerJim Grosbach <grosbach@apple.com>2011-03-11 20:44:08 +0000
commit958108ad14e91d0f778de07e791fce83cd5f20a9 (patch)
tree5f5a0755bde7c1dcfc4b6b824ea682c4b791db3e /utils/TableGen
parent81bb6551e6c6bbc1023750b7aff9ee702442f392 (diff)
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ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
as for VDUP32d and VDUP32q, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
-rw-r--r--utils/TableGen/ARMDecoderEmitter.cpp6
1 files changed, 0 insertions, 6 deletions
diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp
index cae039f..34123f4 100644
--- a/utils/TableGen/ARMDecoderEmitter.cpp
+++ b/utils/TableGen/ARMDecoderEmitter.cpp
@@ -1632,12 +1632,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
Name == "BLX_pred" || Name == "TPsoft")
return false;
- // Ignore VDUPf[d|q] instructions known to conflict with VDUP32[d-q] for
- // decoding. The instruction duplicates an element from an ARM core
- // register into every element of the destination vector. There is no
- // distinction between data types.
- if (Name == "VDUPfd" || Name == "VDUPfq") return false;
-
// A8-598: VEXT
// Vector Extract extracts elements from the bottom end of the second
// operand vector and the top end of the first, concatenates them and