Machine model: allow itineraries to be shared by different processor models.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159959 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 0 deletions

diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp
index 48dbdc2..39055c0 100644
--- a/utils/TableGen/SubtargetEmitter.cpp
+++ b/utils/TableGen/SubtargetEmitter.cpp
@@ -336,10 +336,16 @@ EmitStageAndOperandCycleData(raw_ostream &OS,
                              std::vector<std::vector<InstrItinerary> >
                                &ProcItinLists) {
 
+  // Multiple processor models may share an itinerary record. Emit it once.
+  SmallPtrSet<Record*, 8> ItinsDefSet;
+
   // Emit functional units for all the itineraries.
   for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
          PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
 
+    if (!ItinsDefSet.insert(PI->ItinsDef))
+      continue;
+
     std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU");
     if (FUs.empty())
       continue;
@@ -508,12 +514,18 @@ void SubtargetEmitter::
 EmitItineraries(raw_ostream &OS,
                 std::vector<std::vector<InstrItinerary> > &ProcItinLists) {
 
+  // Multiple processor models may share an itinerary record. Emit it once.
+  SmallPtrSet<Record*, 8> ItinsDefSet;
+
   // For each processor's machine model
   std::vector<std::vector<InstrItinerary> >::iterator
       ProcItinListsIter = ProcItinLists.begin();
   for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
          PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
+
     Record *ItinsDef = PI->ItinsDef;
+    if (!ItinsDefSet.insert(ItinsDef))
+      continue;
 
     // Get processor itinerary name
     const std::string &Name = ItinsDef->getName();