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| author | Craig Topper <craig.topper@gmail.com> | 2011-12-30 06:23:39 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2011-12-30 06:23:39 +0000 |
| commit | 06f554d06ab0f9390d04bcbaabb76f572d940249 (patch) | |
| tree | 57e6926f50790b141be81683d379a4429a7e64ae /utils | |
| parent | e6a3a2990e3f783c906e9db58e55439cb06f9fa5 (diff) | |
| download | external_llvm-06f554d06ab0f9390d04bcbaabb76f572d940249.zip external_llvm-06f554d06ab0f9390d04bcbaabb76f572d940249.tar.gz external_llvm-06f554d06ab0f9390d04bcbaabb76f572d940249.tar.bz2 | |
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index b8b282a..385e579 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -559,7 +559,7 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { bool hasFROperands = false; - assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); + assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) { if (OperandList[operandIndex].Constraints.size()) { @@ -678,7 +678,7 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { // Operand 3 (optional) is an immediate. if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix) - assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); else assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && @@ -699,7 +699,9 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { if (HasVEX_4VOp3Prefix) HANDLE_OPERAND(vvvvRegister) - HANDLE_OPTIONAL(immediate) + if (!HasMemOp4Prefix) + HANDLE_OPTIONAL(immediate) + HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 break; case X86Local::MRMSrcMem: // Operand 1 is a register operand in the Reg/Opcode field. @@ -708,7 +710,7 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { // Operand 3 (optional) is an immediate. if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix) - assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); else assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && @@ -729,7 +731,9 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { if (HasVEX_4VOp3Prefix) HANDLE_OPERAND(vvvvRegister) - HANDLE_OPTIONAL(immediate) + if (!HasMemOp4Prefix) + HANDLE_OPTIONAL(immediate) + HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 break; case X86Local::MRM0r: case X86Local::MRM1r: |