aboutsummaryrefslogtreecommitdiffstats
path: root/utils
diff options
context:
space:
mode:
authorOwen Anderson <resistor@mac.com>2011-04-28 17:51:45 +0000
committerOwen Anderson <resistor@mac.com>2011-04-28 17:51:45 +0000
commit4cdcb4772d95b9e801a0f3cd43776cef3af3b530 (patch)
tree221589eb68e02aa996e783243c7f21e5dc0c3aa1 /utils
parentd78bfbc6bb5342c2256bea0834613b02448ec74d (diff)
downloadexternal_llvm-4cdcb4772d95b9e801a0f3cd43776cef3af3b530.zip
external_llvm-4cdcb4772d95b9e801a0f3cd43776cef3af3b530.tar.gz
external_llvm-4cdcb4772d95b9e801a0f3cd43776cef3af3b530.tar.bz2
Fix a bug in tblgen that caused incorrect encodings on instructions that specified operands with "bit" instead of "bits<1>".
Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question. <rdar://problem/9345702> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130410 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r--utils/TableGen/CodeEmitterGen.cpp6
1 files changed, 5 insertions, 1 deletions
diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index 957dd19..9d4dc5c4 100644
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -63,10 +63,14 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
// return the variable bit position. Otherwise return -1.
int CodeEmitterGen::getVariableBit(const std::string &VarName,
BitsInit *BI, int bit) {
- if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit)))
+ if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
if (VarInit *VI = dynamic_cast<VarInit*>(VBI->getVariable()))
if (VI->getName() == VarName)
return VBI->getBitNum();
+ } else if (VarInit *VI = dynamic_cast<VarInit*>(BI->getBit(bit))) {
+ if (VI->getName() == VarName)
+ return 0;
+ }
return -1;
}