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author | Dan Gohman <gohman@apple.com> | 2009-09-25 20:36:54 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-09-25 20:36:54 +0000 |
commit | 4e3bb1bc735783b73f2dcca82c86b7faca1a87e8 (patch) | |
tree | bc66c4b4bc5955aa33a7c6fb19c0163ef070b08a /utils | |
parent | 61fda0d889b3578fe435455679182c231a649aac (diff) | |
download | external_llvm-4e3bb1bc735783b73f2dcca82c86b7faca1a87e8.zip external_llvm-4e3bb1bc735783b73f2dcca82c86b7faca1a87e8.tar.gz external_llvm-4e3bb1bc735783b73f2dcca82c86b7faca1a87e8.tar.bz2 |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/DAGISelEmitter.cpp | 29 |
1 files changed, 11 insertions, 18 deletions
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 2488a96..dcf64e4 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -1135,24 +1135,18 @@ public: emitCode("}"); } - // Generate MemOperandSDNodes nodes for each memory accesses covered by + // Populate MemRefs with entries for each memory accesses covered by // this pattern. - if (II.mayLoad | II.mayStore) { - std::vector<std::string>::const_iterator mi, mie; - for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) { - std::string LSIName = "LSI_" + *mi; - emitCode("SDValue " + LSIName + " = " - "CurDAG->getMemOperand(cast<MemSDNode>(" + - *mi + ")->getMemOperand());"); - if (GenDebug) { - emitCode("CurDAG->setSubgraphColor(" + LSIName +".getNode(), \"yellow\");"); - emitCode("CurDAG->setSubgraphColor(" + LSIName +".getNode(), \"black\");"); - } - if (IsVariadic) - emitCode("Ops" + utostr(OpsNo) + ".push_back(" + LSIName + ");"); - else - AllOps.push_back(LSIName); - } + if (isRoot && !LSI.empty()) { + std::string MemRefs = "MemRefs" + utostr(OpsNo); + emitCode("MachineSDNode::mmo_iterator " + MemRefs + " = " + "MF->allocateMemRefsArray(" + utostr(LSI.size()) + ");"); + for (unsigned i = 0, e = LSI.size(); i != e; ++i) + emitCode(MemRefs + "[" + utostr(i) + "] = " + "cast<MemSDNode>(" + LSI[i] + ")->getMemOperand();"); + After.push_back("cast<MachineSDNode>(ResNode)->setMemRefs(" + + MemRefs + ", " + MemRefs + " + " + utostr(LSI.size()) + + ");"); } if (NodeHasChain) { @@ -1965,7 +1959,6 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) { << " assert(!N.isMachineOpcode() && \"Node already selected!\");\n" << " break;\n" << " case ISD::EntryToken: // These nodes remain the same.\n" - << " case ISD::MEMOPERAND:\n" << " case ISD::BasicBlock:\n" << " case ISD::Register:\n" << " case ISD::HANDLENODE:\n" |