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authorHal Finkel <hfinkel@anl.gov>2013-04-18 22:15:08 +0000
committerHal Finkel <hfinkel@anl.gov>2013-04-18 22:15:08 +0000
commit860c08cad5b7c1359123bb2b0e74df4b6e48a15c (patch)
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Implement optimizeCompareInstr for PPC
Many PPC instructions have a so-called 'record form' which stores to a specific condition register the result of comparing the result of the instruction with zero (always as a signed comparison). For integer operations on PPC64, this is always a 64-bit comparison. This implementation is derived from the implementation in the ARM backend; there are some differences because PPC condition registers are allocatable virtual registers (although the record forms always use a specific one), and we look for a matching subtraction instruction after the compare (but before the first use) in addition to before it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
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