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author | Bill Wendling <isanbard@gmail.com> | 2008-05-28 22:54:52 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2008-05-28 22:54:52 +0000 |
commit | aa25bb1320b4e94d2f90326ab73f2a42e5a4c3b7 (patch) | |
tree | 4689ca3c0b6ee971d3aef6ec8536642eefb377a8 /utils | |
parent | 023520fc86b25d1db939d9de179118f684948d1c (diff) | |
download | external_llvm-aa25bb1320b4e94d2f90326ab73f2a42e5a4c3b7.zip external_llvm-aa25bb1320b4e94d2f90326ab73f2a42e5a4c3b7.tar.gz external_llvm-aa25bb1320b4e94d2f90326ab73f2a42e5a4c3b7.tar.bz2 |
Add a flag to indicate that an instruction is as cheap (or cheaper) than a move
instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/CodeGenInstruction.cpp | 1 | ||||
-rw-r--r-- | utils/TableGen/CodeGenInstruction.h | 5 | ||||
-rw-r--r-- | utils/TableGen/InstrInfoEmitter.cpp | 27 |
3 files changed, 19 insertions, 14 deletions
diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp index 53daf9d..37c2069 100644 --- a/utils/TableGen/CodeGenInstruction.cpp +++ b/utils/TableGen/CodeGenInstruction.cpp @@ -99,6 +99,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) hasSideEffects = R->getValueAsBit("hasSideEffects"); mayHaveSideEffects = R->getValueAsBit("mayHaveSideEffects"); neverHasSideEffects = R->getValueAsBit("neverHasSideEffects"); + isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove"); hasOptionalDef = false; isVariadic = false; diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h index 9bfd432..0727e38 100644 --- a/utils/TableGen/CodeGenInstruction.h +++ b/utils/TableGen/CodeGenInstruction.h @@ -102,7 +102,10 @@ namespace llvm { bool hasCtrlDep; bool isNotDuplicable; bool hasOptionalDef; - bool hasSideEffects, mayHaveSideEffects, neverHasSideEffects; + bool hasSideEffects; + bool mayHaveSideEffects; + bool neverHasSideEffects; + bool isAsCheapAsAMove; /// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar", /// where $foo is a whole operand and $foo.bar refers to a suboperand. diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index 57d72b4..028fbeb 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -208,26 +208,27 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, << ",\t\"" << Inst.TheDef->getName() << "\", 0"; // Emit all of the target indepedent flags... - if (Inst.isReturn) OS << "|(1<<TID::Return)"; - if (Inst.isBranch) OS << "|(1<<TID::Branch)"; - if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)"; - if (Inst.isBarrier) OS << "|(1<<TID::Barrier)"; - if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)"; - if (Inst.isCall) OS << "|(1<<TID::Call)"; - if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)"; - if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)"; - if (Inst.mayStore) OS << "|(1<<TID::MayStore)"; - if (Inst.isPredicable) OS << "|(1<<TID::Predicable)"; + if (Inst.isReturn) OS << "|(1<<TID::Return)"; + if (Inst.isBranch) OS << "|(1<<TID::Branch)"; + if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)"; + if (Inst.isBarrier) OS << "|(1<<TID::Barrier)"; + if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)"; + if (Inst.isCall) OS << "|(1<<TID::Call)"; + if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)"; + if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)"; + if (Inst.mayStore) OS << "|(1<<TID::MayStore)"; + if (Inst.isPredicable) OS << "|(1<<TID::Predicable)"; if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)"; - if (Inst.isCommutable) OS << "|(1<<TID::Commutable)"; - if (Inst.isTerminator) OS << "|(1<<TID::Terminator)"; + if (Inst.isCommutable) OS << "|(1<<TID::Commutable)"; + if (Inst.isTerminator) OS << "|(1<<TID::Terminator)"; if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)"; if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)"; if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)"; if (Inst.usesCustomDAGSchedInserter) OS << "|(1<<TID::UsesCustomDAGSchedInserter)"; if (Inst.isVariadic) OS << "|(1<<TID::Variadic)"; - if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)"; + if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)"; + if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)"; OS << ", 0"; // Emit all of the target-specific flags... |