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authorChris Lattner <sabre@nondot.org>2005-10-19 01:55:23 +0000
committerChris Lattner <sabre@nondot.org>2005-10-19 01:55:23 +0000
commitab1bf27be5a3045ef8174eebd74f7630a7c58d3b (patch)
tree9491f60ad9325788937749bbc1451a12cff81437 /utils
parent14c09b81ead8fe8b754fca2d0a8237cb810b37d6 (diff)
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Asserting here is to violent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23814 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r--utils/TableGen/DAGISelEmitter.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index d0dc799..12ca95f 100644
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -462,7 +462,9 @@ static unsigned char getIntrinsicType(Record *R, bool NotRegisters,
// Pattern fragment types will be resolved when they are inlined.
return MVT::isUnknown;
} else if (R->isSubClassOf("Register")) {
- assert(0 && "Explicit registers not handled here yet!\n");
+ //const CodeGenTarget &T = TP.getDAGISelEmitter().getTargetInfo();
+ // TODO: if a register appears in exactly one regclass, we could use that
+ // type info.
return MVT::isUnknown;
} else if (R->isSubClassOf("ValueType")) {
// Using a VTSDNode.