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author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-11 23:50:47 +0000 |
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committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-11 23:50:47 +0000 |
commit | c902a59f4c786a2a047f0b4c964a93108f248915 (patch) | |
tree | 5d8244c57782653dadf7e4e24ce53a83ff0cd01d /utils | |
parent | 771d90ff4316d3557bfb1d6d500529d290b808d0 (diff) | |
download | external_llvm-c902a59f4c786a2a047f0b4c964a93108f248915.zip external_llvm-c902a59f4c786a2a047f0b4c964a93108f248915.tar.gz external_llvm-c902a59f4c786a2a047f0b4c964a93108f248915.tar.bz2 |
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
Introduce the VEX_X field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 5fe2bfe..19b51cb 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -535,7 +535,8 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { HANDLE_OPERAND(rmRegister) if (HasVEX_4VPrefix) - // FIXME: encoding of registers in AVX is in 1's complement form. + // FIXME: In AVX, the register below becomes the one encoded + // in ModRMVEX and the one above the one in the VEX.VVVV field HANDLE_OPTIONAL(rmRegister) else HANDLE_OPTIONAL(immediate) @@ -547,6 +548,12 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && "Unexpected number of operands for MRMSrcMemFrm"); HANDLE_OPERAND(roRegister) + + if (HasVEX_4VPrefix) + // FIXME: In AVX, the register below becomes the one encoded + // in ModRMVEX and the one above the one in the VEX.VVVV field + HANDLE_OPTIONAL(rmRegister) + HANDLE_OPERAND(memory) HANDLE_OPTIONAL(immediate) break; |