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authorChris Lattner <sabre@nondot.org>2010-11-01 23:57:23 +0000
committerChris Lattner <sabre@nondot.org>2010-11-01 23:57:23 +0000
commite66b7ebfb426c7ed9bc911e9708321e2d8510b41 (patch)
tree8f71860fec4d4346900c611cd46e726f8a6571e4 /utils
parent9af3d1c0dc2250793ada1ca6cfa98e9f1253f7f9 (diff)
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fix computation of ambiguous instructions to not ignore the mnemonic.
FWIW, X86 has 254 ambiguous instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117979 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r--utils/TableGen/AsmMatcherEmitter.cpp10
1 files changed, 7 insertions, 3 deletions
diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp
index 7f653a3..532a7b5 100644
--- a/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/utils/TableGen/AsmMatcherEmitter.cpp
@@ -411,6 +411,10 @@ struct MatchableInfo {
/// ambiguously match the same set of operands as \arg RHS (without being a
/// strictly superior match).
bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
+ // The primary comparator is the instruction mnemonic.
+ if (Tokens[0] != RHS.Tokens[0])
+ return false;
+
// The number of operands is unambiguous.
if (Operands.size() != RHS.Operands.size())
return false;
@@ -849,8 +853,8 @@ BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
}
void AsmMatcherInfo::BuildOperandClasses() {
- std::vector<Record*> AsmOperands;
- AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass");
+ std::vector<Record*> AsmOperands =
+ Records.getAllDerivedDefinitions("AsmOperandClass");
// Pre-populate AsmOperandClasses map.
for (std::vector<Record*>::iterator it = AsmOperands.begin(),
@@ -1127,7 +1131,7 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
}
}
- std::sort(MIOperandList.begin(), MIOperandList.end());
+ array_pod_sort(MIOperandList.begin(), MIOperandList.end());
// Compute the total number of operands.
unsigned NumMIOperands = 0;