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-rw-r--r--include/llvm/Target/TargetInstrInfo.h24
-rw-r--r--lib/CodeGen/LiveIntervalAnalysis.cpp2
-rw-r--r--lib/CodeGen/MachineLICM.cpp26
-rw-r--r--lib/Target/X86/X86InstrInfo.cpp2
-rw-r--r--lib/Target/X86/X86InstrInfo.h2
-rw-r--r--tools/Makefile4
-rw-r--r--utils/emacs/tablegen-mode.el38
7 files changed, 49 insertions, 49 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 2f2f4cd..a0596e4 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -288,24 +288,24 @@ public:
return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
}
- /// hasNoSideEffects - Return true if the instruction is trivially
+ /// isTriviallyReMaterializable - Return true if the instruction is trivially
/// rematerializable, meaning it has no side effects and requires no operands
/// that aren't always available.
- bool hasNoSideEffects(MachineInstr *MI) const {
+ bool isTriviallyReMaterializable(MachineInstr *MI) const {
return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) &&
- isTriviallyReMaterializable(MI);
+ isReallyTriviallyReMaterializable(MI);
}
protected:
- /// isTriviallyReMaterializable - For instructions with opcodes for which the
- /// M_REMATERIALIZABLE flag is set, this function tests whether the
- /// instruction itself is actually trivially rematerializable, considering its
- /// operands. This is used for targets that have instructions that are only
- /// trivially rematerializable for specific uses. This predicate must return
- /// false if the instruction has any side effects other than producing a
- /// value, or if it requres any address registers that are not always
- /// available.
- virtual bool isTriviallyReMaterializable(MachineInstr *MI) const {
+ /// isReallyTriviallyReMaterializable - For instructions with opcodes for
+ /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
+ /// instruction itself is actually trivially rematerializable, considering
+ /// its operands. This is used for targets that have instructions that are
+ /// only trivially rematerializable for specific uses. This predicate must
+ /// return false if the instruction has any side effects other than
+ /// producing a value, or if it requres any address registers that are not
+ /// always available.
+ virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
return true;
}
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index f4144e3..d151da3 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -613,7 +613,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
return false;
isLoad = false;
- if (tii_->hasNoSideEffects(MI)) {
+ if (tii_->isTriviallyReMaterializable(MI)) {
isLoad = MI->getInstrDescriptor()->Flags & M_LOAD_FLAG;
return true;
}
diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index 0f8c01c..c66e062 100644
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -39,7 +39,7 @@ namespace {
cl::desc("Perform loop-invariant code motion on machine code"));
}
-STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loop");
+STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
namespace {
class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
@@ -93,11 +93,11 @@ namespace {
///
void MapVirtualRegisterDefs(const MachineFunction &MF);
- /// isInSubLoop - A little predicate that returns true if the specified
+ /// IsInSubLoop - A little predicate that returns true if the specified
/// basic block is in a subloop of the current one, not the current one
/// itself.
///
- bool isInSubLoop(MachineBasicBlock *BB) {
+ bool IsInSubLoop(MachineBasicBlock *BB) {
assert(CurLoop->contains(BB) && "Only valid if BB is IN the loop");
for (MachineLoop::iterator
@@ -120,7 +120,7 @@ namespace {
if (TID->ImplicitUses || !I.getNumOperands()) return false;
MachineOpCode Opcode = TID->Opcode;
- return TII->hasNoSideEffects(&I) &&
+ return TII->isTriviallyReMaterializable(&I) &&
// FIXME: Below necessary?
!(TII->isReturn(Opcode) ||
TII->isTerminatorInstr(Opcode) ||
@@ -132,12 +132,12 @@ namespace {
TII->isStore(Opcode));
}
- /// isLoopInvariantInst - Returns true if the instruction is loop
+ /// IsLoopInvariantInst - Returns true if the instruction is loop
/// invariant. I.e., all virtual register operands are defined outside of
/// the loop, physical registers aren't accessed (explicitly or implicitly),
/// and the instruction is hoistable.
///
- bool isLoopInvariantInst(MachineInstr &I);
+ bool IsLoopInvariantInst(MachineInstr &I);
/// FindPredecessors - Get all of the predecessors of the loop that are not
/// back-edges.
@@ -246,7 +246,7 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
// Only need to process the contents of this block if it is not part of a
// subloop (which would already have been processed).
- if (!isInSubLoop(BB))
+ if (!IsInSubLoop(BB))
for (MachineBasicBlock::iterator
I = BB->begin(), E = BB->end(); I != E; ) {
MachineInstr &MI = *I++;
@@ -263,12 +263,12 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
HoistRegion(Children[I]);
}
-/// isLoopInvariantInst - Returns true if the instruction is loop
+/// IsLoopInvariantInst - Returns true if the instruction is loop
/// invariant. I.e., all virtual register operands are defined outside of the
/// loop, physical registers aren't accessed (explicitly or implicitly), and the
/// instruction is hoistable.
///
-bool MachineLICM::isLoopInvariantInst(MachineInstr &I) {
+bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
if (!CanHoistInst(I)) return false;
// The instruction is loop invariant if all of its operands are loop-invariant
@@ -300,7 +300,7 @@ bool MachineLICM::isLoopInvariantInst(MachineInstr &I) {
/// that is safe to hoist, this instruction is called to do the dirty work.
///
void MachineLICM::Hoist(MachineInstr &MI) {
- if (!isLoopInvariantInst(MI)) return;
+ if (!IsLoopInvariantInst(MI)) return;
std::vector<MachineBasicBlock*> Preds;
@@ -316,9 +316,9 @@ void MachineLICM::Hoist(MachineInstr &MI) {
// the loop header.
MachineBasicBlock *MBB = Preds.front();
- // FIXME: We are assuming at first that the basic blocks coming into this loop
- // have only one successor each. This isn't the case in general because we
- // haven't broken critical edges or added preheaders.
+ // FIXME: We are assuming at first that the basic block coming into this loop
+ // has only one successor. This isn't the case in general because we haven't
+ // broken critical edges or added preheaders.
if (MBB->succ_size() != 1) return;
assert(*MBB->succ_begin() == CurLoop->getHeader() &&
"The predecessor doesn't feed directly into the loop header!");
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 880e2fd..9d5e637 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -116,7 +116,7 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
}
-bool X86InstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const {
+bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: break;
case X86::MOV8rm:
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 1e6aaf3..2694481 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -239,7 +239,7 @@ public:
unsigned& destReg) const;
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
- bool isTriviallyReMaterializable(MachineInstr *MI) const;
+ bool isReallyTriviallyReMaterializable(MachineInstr *MI) const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
diff --git a/tools/Makefile b/tools/Makefile
index 703a2e9..e642b35 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -16,8 +16,8 @@ PARALLEL_DIRS := llvm-config \
llc llvm-ranlib llvm-ar llvm-nm \
llvm-ld llvmc llvm-prof llvm-link \
lli gccas gccld llvm-extract llvm-db llvm2cpp \
- bugpoint llvm-bcanalyzer llvm-stub
-
+ bugpoint llvm-bcanalyzer llvm-stub cfe
+
include $(LEVEL)/Makefile.config
diff --git a/utils/emacs/tablegen-mode.el b/utils/emacs/tablegen-mode.el
index af33cbd..e180915 100644
--- a/utils/emacs/tablegen-mode.el
+++ b/utils/emacs/tablegen-mode.el
@@ -16,7 +16,7 @@
(defvar tablegen-font-lock-keywords
(let ((kw (mapconcat 'identity
- '("class" "def" "defm" "field" "in" "include"
+ '("class" "defm" "def" "field" "include" "in"
"let" "multiclass")
"\\|"))
(type-kw (mapconcat 'identity
@@ -49,15 +49,16 @@
;; ---------------------- Syntax table ---------------------------
;; Shamelessly ripped from jasmin.el
-;; URL: http://www.neilvandyke.org/jasmin-emacs/jasmin.el.html
+;; URL: http://www.neilvandyke.org/jasmin-emacs/jasmin.el
(if (not tablegen-mode-syntax-table)
(progn
(setq tablegen-mode-syntax-table (make-syntax-table))
- (mapcar (function (lambda (n)
- (modify-syntax-entry (aref n 0)
- (aref n 1)
- tablegen-mode-syntax-table)))
+ (mapcar (function
+ (lambda (n)
+ (modify-syntax-entry (aref n 0)
+ (aref n 1)
+ tablegen-mode-syntax-table)))
'(
;; whitespace (` ')
[?\^m " "]
@@ -66,8 +67,6 @@
[?\t " "]
[?\ " "]
;; word constituents (`w')
- ;;[?< "w"]
- ;;[?> "w"]
[?\% "w"]
;;[?_ "w "]
;; comments
@@ -78,15 +77,17 @@
;; symbol constituents (`_')
;; punctuation (`.')
;; open paren (`(')
- [?\( "("]
- [?\[ "("]
- [?\{ "("]
+ [?\( "("]
+ [?\[ "("]
+ [?\{ "("]
+ [?\< "("]
;; close paren (`)')
- [?\) ")"]
- [?\] ")"]
- [?\} ")"]
+ [?\) ")"]
+ [?\] ")"]
+ [?\} ")"]
+ [?\> ")"]
;; string quote ('"')
- [?\" "\""]
+ [?\" "\""]
))))
;; --------------------- Abbrev table -----------------------------
@@ -101,11 +102,10 @@
(if (not tablegen-mode-map)
() ; Do not change the keymap if it is already set up.
(setq tablegen-mode-map (make-sparse-keymap))
- (define-key tablegen-mode-map "\t" 'tab-to-tab-stop)
+ (define-key tablegen-mode-map "\t" 'tab-to-tab-stop)
(define-key tablegen-mode-map "\es" 'center-line)
(define-key tablegen-mode-map "\eS" 'center-paragraph))
-
(defun tablegen-mode ()
"Major mode for editing TableGen description files.
\\{tablegen-mode-map}
@@ -115,10 +115,10 @@
(use-local-map tablegen-mode-map) ; Provides the local keymap.
(setq major-mode 'tablegen-mode)
- (make-local-variable 'font-lock-defaults)
+ (make-local-variable 'font-lock-defaults)
(setq major-mode 'tablegen-mode ; This is how describe-mode
; finds the doc string to print.
- mode-name "TableGen" ; This name goes into the modeline.
+ mode-name "TableGen" ; This name goes into the modeline.
font-lock-defaults `(tablegen-font-lock-keywords))
(setq local-abbrev-table tablegen-mode-abbrev-table)
generated by cgit v1.1 at 2024-12-22 23:07:18 +0000