diff options
32 files changed, 161 insertions, 127 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index a5ea6df..bec37a6 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -88,11 +88,11 @@ protected: } public: - /// Return true if the instruction is a register to register move - /// and leave the source and dest operands in the passed parameters. + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. virtual bool isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg) const { + unsigned& SrcReg, unsigned& DstReg, + unsigned& SrcSubIdx, unsigned& DstSubIdx) const { return false; } diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 2259589..8cd82a6 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -298,8 +298,8 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li, if (index == end) break; MachineInstr *MI = getInstructionFromIndex(index); - unsigned SrcReg, DstReg; - if (tii_->isMoveInstr(*MI, SrcReg, DstReg)) + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) if (SrcReg == li.reg || DstReg == li.reg) continue; for (unsigned i = 0; i != MI->getNumOperands(); ++i) { @@ -396,10 +396,10 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, defIndex = getUseIndex(MIIdx); VNInfo *ValNo; MachineInstr *CopyMI = NULL; - unsigned SrcReg, DstReg; + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - tii_->isMoveInstr(*mi, SrcReg, DstReg)) + tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = mi; // Earlyclobbers move back one. ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator); @@ -551,10 +551,10 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, VNInfo *ValNo; MachineInstr *CopyMI = NULL; - unsigned SrcReg, DstReg; + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - tii_->isMoveInstr(*mi, SrcReg, DstReg)) + tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = mi; ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator); @@ -653,10 +653,10 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, getOrCreateInterval(MO.getReg())); else if (allocatableRegs_[MO.getReg()]) { MachineInstr *CopyMI = NULL; - unsigned SrcReg, DstReg; + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - tii_->isMoveInstr(*MI, SrcReg, DstReg)) + tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = MI; handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, getOrCreateInterval(MO.getReg()), CopyMI); @@ -844,8 +844,8 @@ unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const { } else if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG) return VNI->copy->getOperand(2).getReg(); - unsigned SrcReg, DstReg; - if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg)) + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg, SrcSubReg, DstSubReg)) return SrcReg; assert(0 && "Unrecognized copy instruction!"); return 0; diff --git a/lib/CodeGen/PreAllocSplitting.cpp b/lib/CodeGen/PreAllocSplitting.cpp index 2f49e25..6b37637 100644 --- a/lib/CodeGen/PreAllocSplitting.cpp +++ b/lib/CodeGen/PreAllocSplitting.cpp @@ -846,9 +846,9 @@ void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) { VNInfo* NewVN = LI->getNextValue(DefIdx, 0, Alloc); // If the def is a move, set the copy field. - unsigned source, dest; - if (TII->isMoveInstr(*DI, source, dest)) - if (dest == LI->reg) + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) + if (DstReg == LI->reg) NewVN->copy = &*DI; NewVNs[&*DI] = NewVN; diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp index 73845db..584aa7c 100644 --- a/lib/CodeGen/RegAllocBigBlock.cpp +++ b/lib/CodeGen/RegAllocBigBlock.cpp @@ -823,8 +823,9 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { } // Finally, if this is a noop copy instruction, zap it. - unsigned SrcReg, DstReg; - if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (TII.isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) && + SrcReg == DstReg) MBB.erase(MI); } diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 96f8ab4..a944461 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -253,8 +253,9 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) { if (!vni->def || vni->def == ~1U || vni->def == ~0U) return Reg; MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); - unsigned SrcReg, DstReg; - if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (!CopyMI || + !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) return Reg; if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { if (!vrm_->isAssignedReg(SrcReg)) @@ -695,8 +696,9 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) VNInfo *vni = cur->begin()->valno; if (vni->def && vni->def != ~1U && vni->def != ~0U) { MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); - unsigned SrcReg, DstReg; - if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) { + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (CopyMI && + tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) { unsigned Reg = 0; if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) Reg = SrcReg; diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index bf4e205..acd3dde 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -960,8 +960,9 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { } // Finally, if this is a noop copy instruction, zap it. - unsigned SrcReg, DstReg; - if (TII->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) && + SrcReg == DstReg) MBB.erase(MI); } diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp index 40f7570..dfee8cf9b 100644 --- a/lib/CodeGen/RegAllocPBQP.cpp +++ b/lib/CodeGen/RegAllocPBQP.cpp @@ -359,10 +359,10 @@ PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() { iItr != iEnd; ++iItr) { const MachineInstr *instr = &*iItr; - unsigned srcReg, dstReg; + unsigned srcReg, dstReg, srcSubReg, dstSubReg; // If this isn't a copy then continue to the next instruction. - if (!tii->isMoveInstr(*instr, srcReg, dstReg)) + if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg)) continue; // If the registers are already the same our job is nice and easy. diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 547cd8d..ca0cd6e 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -189,9 +189,9 @@ static void EmitLiveInCopy(MachineBasicBlock *MBB, // don't coalesce. Also, only coalesce away a virtual register to virtual // register copy. bool Coalesced = false; - unsigned SrcReg, DstReg; + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (NumUses == 1 && - TII.isMoveInstr(*UseMI, SrcReg, DstReg) && + TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && TargetRegisterInfo::isVirtualRegister(DstReg)) { VirtReg = DstReg; Coalesced = true; diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index 09b610c..637d74b 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -386,8 +386,8 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, else BKills.push_back(li_->getUseIndex(UseIdx)+1); } - unsigned SrcReg, DstReg; - if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) continue; if (DstReg == IntB.reg) { // This copy will become a noop. If it's defining a new val#, @@ -563,8 +563,9 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, if (OldSubIdx) UseDstReg = tri_->getSubReg(DstReg, OldSubIdx); - unsigned CopySrcReg, CopyDstReg; - if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) && + unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx; + if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg, + CopySrcSubIdx, CopyDstSubIdx) && CopySrcReg != CopyDstReg && CopySrcReg == SrcReg && CopyDstReg != UseDstReg) { // If the use is a copy and it won't be coalesced away, and its source @@ -595,9 +596,10 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, // After updating the operand, check if the machine instruction has // become a copy. If so, update its val# information. const TargetInstrDesc &TID = UseMI->getDesc(); - unsigned CopySrcReg, CopyDstReg; + unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx; if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 && - tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) && + tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg, + CopySrcSubIdx, CopyDstSubIdx) && CopySrcReg != CopyDstReg && (TargetRegisterInfo::isVirtualRegister(CopyDstReg) || allocatableRegs_[CopyDstReg])) { @@ -818,8 +820,8 @@ SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li, // of last use. LastUse->setIsKill(); removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_); - unsigned SrcReg, DstReg; - if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) && + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && DstReg == li.reg) { // Last use is itself an identity code. int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_); @@ -873,8 +875,8 @@ bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI, if (ULR == li.end() || ULR->valno != LR->valno) continue; // If the use is not a use, then it's not safe to coalesce the move. - unsigned SrcReg, DstReg; - if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) { + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG && UseMI->getOperand(1).getReg() == li.reg) continue; @@ -911,8 +913,9 @@ void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li, if (ULR == li.end() || ULR->valno != VNI) continue; // If the use is a copy, turn it into an identity copy. - unsigned SrcReg, DstReg; - if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) { + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && + SrcReg == li.reg) { // Each use MI may have multiple uses of this register. Change them all. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); @@ -1123,8 +1126,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI; - unsigned SrcReg; - unsigned DstReg; + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG; bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG; unsigned SubIdx = 0; @@ -1139,7 +1141,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { } DstReg = CopyMI->getOperand(0).getReg(); SrcReg = CopyMI->getOperand(2).getReg(); - } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) { + } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){ assert(0 && "Unrecognized copy instruction!"); return false; } @@ -1428,10 +1430,11 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { if (!vni->def || vni->def == ~1U || vni->def == ~0U) continue; MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); - unsigned NewSrcReg, NewDstReg; + unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx; if (CopyMI && JoinedCopies.count(CopyMI) == 0 && - tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) { + tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg, + NewSrcSubIdx, NewDstSubIdx)) { unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB); JoinQueue->push(CopyRec(CopyMI, LoopDepth, isBackEdgeCopy(CopyMI, DstReg))); @@ -1570,8 +1573,9 @@ bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li, // It's a sub-register live interval, we may not have precise information. // Re-compute it. MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start); - unsigned SrcReg, DstReg; - if (DefMI && tii_->isMoveInstr(*DefMI, SrcReg, DstReg) && + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (DefMI && + tii_->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && DstReg == li.reg && SrcReg == Reg) { // Cache computed info. LR->valno->def = LR->start; @@ -2070,14 +2074,14 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, MachineInstr *Inst = MII++; // If this isn't a copy nor a extract_subreg, we can't join intervals. - unsigned SrcReg, DstReg; + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { DstReg = Inst->getOperand(0).getReg(); SrcReg = Inst->getOperand(1).getReg(); } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) { DstReg = Inst->getOperand(0).getReg(); SrcReg = Inst->getOperand(2).getReg(); - } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) + } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) continue; bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); @@ -2243,8 +2247,9 @@ SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, E = mri_->use_end(); I != E; ++I) { MachineOperand &Use = I.getOperand(); MachineInstr *UseMI = Use.getParent(); - unsigned SrcReg, DstReg; - if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg) + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && + SrcReg == DstReg) // Ignore identity copies. continue; unsigned Idx = li_->getInstructionIndex(UseMI); @@ -2269,8 +2274,9 @@ SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, return NULL; // Ignore identity copies. - unsigned SrcReg, DstReg; - if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)) + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && + SrcReg == DstReg)) for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { MachineOperand &Use = MI->getOperand(i); if (Use.isReg() && Use.isUse() && Use.getReg() && @@ -2389,10 +2395,10 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); mii != mie; ) { MachineInstr *MI = mii; - unsigned SrcReg, DstReg; + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; if (JoinedCopies.count(MI)) { // Delete all coalesced copies. - if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) { + if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) && "Unrecognized copy instruction"); @@ -2441,7 +2447,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { } // If the move will be an identity move delete it - bool isMove = tii_->isMoveInstr(*MI, SrcReg, DstReg); + bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx); if (isMove && SrcReg == DstReg) { if (li_->hasInterval(SrcReg)) { LiveInterval &RegInt = li_->getInterval(SrcReg); diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index dab0215..b35fc2c 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -1753,8 +1753,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { // Check to see if this is a noop copy. If so, eliminate the // instruction before considering the dest reg to be changed. - unsigned Src, Dst; - if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { + unsigned Src, Dst, SrcSR, DstSR; + if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) { ++NumDCE; DOUT << "Removing now-noop copy: " << MI; SmallVector<unsigned, 2> KillRegs; @@ -1840,8 +1840,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // Check to see if this is a noop copy. If so, eliminate the // instruction before considering the dest reg to be changed. { - unsigned Src, Dst; - if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { + unsigned Src, Dst, SrcSR, DstSR; + if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) { ++NumDCE; DOUT << "Removing now-noop copy: " << MI; InvalidateKills(MI, RegKills, KillOps); diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index bd16af0..3d1e512 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -51,7 +51,10 @@ const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const { /// leave the source and dest operands in the passed parameters. /// bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg) const { + unsigned &SrcReg, unsigned &DstReg, + unsigned& SrcSubIdx, unsigned& DstSubIdx) const { + SrcSubIdx = DstSubIdx = 0; // No sub-registers. + unsigned oc = MI.getOpcode(); switch (oc) { default: diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index 7afeb84..fda057d 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -155,11 +155,12 @@ public: /// This is used for addressing modes. virtual const TargetRegisterClass *getPointerRegClass() const; - /// Return true if the instruction is a register to register move and - /// leave the source and dest operands in the passed parameters. - /// + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg) const; + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; + virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; virtual unsigned isStoreToStackSlot(const MachineInstr *MI, diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index fa8224f..2c7404d 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -25,8 +25,8 @@ AlphaInstrInfo::AlphaInstrInfo() bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg) const { + unsigned& sourceReg, unsigned& destReg, + unsigned& SrcSR, unsigned& DstSR) const { unsigned oc = MI.getOpcode(); if (oc == Alpha::BISr || oc == Alpha::CPYSS || @@ -43,6 +43,7 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { sourceReg = MI.getOperand(1).getReg(); destReg = MI.getOperand(0).getReg(); + SrcSR = DstSR = 0; return true; } } diff --git a/lib/Target/Alpha/AlphaInstrInfo.h b/lib/Target/Alpha/AlphaInstrInfo.h index f04c488..85f5a54 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.h +++ b/lib/Target/Alpha/AlphaInstrInfo.h @@ -30,11 +30,11 @@ public: /// virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and - /// leave the source and dest operands in the passed parameters. - /// + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg) const; + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index fa6e33b..5802eb6 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -64,7 +64,10 @@ SPUInstrInfo::getPointerRegClass() const bool SPUInstrInfo::isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, - unsigned& destReg) const { + unsigned& destReg, + unsigned& SrcSR, unsigned& DstSR) const { + SrcSR = DstSR = 0; // No sub-registers. + // Primarily, ORI and OR are generated by copyRegToReg. But, there are other // cases where we can safely say that what's being done is really a move // (see how PowerPC does this -- it's the model for this code too.) diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h index bc57e15..7bbdfad 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.h +++ b/lib/Target/CellSPU/SPUInstrInfo.h @@ -49,12 +49,11 @@ namespace llvm { /// This is used for addressing modes. virtual const TargetRegisterClass *getPointerRegClass() const; - // Return true if the instruction is a register to register move and - // leave the source and dest operands in the passed parameters. - // - virtual bool isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg) const; + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. + virtual bool isMoveInstr(const MachineInstr &MI, + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index 0a13c68..a3009b2 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -26,8 +26,11 @@ IA64InstrInfo::IA64InstrInfo() bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg) const { + unsigned& sourceReg, + unsigned& destReg, + unsigned& SrcSR, unsigned& DstSR) const { + SrcSR = DstSR = 0; // No sub-registers. + unsigned oc = MI.getOpcode(); if (oc == IA64::MOV || oc == IA64::FMOV) { // TODO: this doesn't detect predicate moves diff --git a/lib/Target/IA64/IA64InstrInfo.h b/lib/Target/IA64/IA64InstrInfo.h index 203f1e8..79236c2 100644 --- a/lib/Target/IA64/IA64InstrInfo.h +++ b/lib/Target/IA64/IA64InstrInfo.h @@ -30,13 +30,11 @@ public: /// virtual const IA64RegisterInfo &getRegisterInfo() const { return RI; } - // - // Return true if the instruction is a register to register move and - // leave the source and dest operands in the passed parameters. - // - virtual bool isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg) const; + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. + virtual bool isMoveInstr(const MachineInstr &MI, + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond) const; diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index e71d26d..daff538 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -30,8 +30,11 @@ static bool isZeroImm(const MachineOperand &op) { /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. bool MipsInstrInfo:: -isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const +isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const { + SrcSubIdx = DstSubIdx = 0; // No sub-registers. + // addu $dst, $src, $zero || addu $dst, $zero, $src // or $dst, $src, $zero || or $dst, $zero, $src if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) { diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 4302bfd..f633776 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -141,11 +141,11 @@ public: /// virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and - /// leave the source and dest operands in the passed parameters. - /// + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg) const; + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of diff --git a/lib/Target/PIC16/PIC16InstrInfo.cpp b/lib/Target/PIC16/PIC16InstrInfo.cpp index 5fe5dac..47ac6d3 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.cpp +++ b/lib/Target/PIC16/PIC16InstrInfo.cpp @@ -138,8 +138,9 @@ bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB, } bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, - unsigned &DestReg) const { + unsigned &SrcReg, unsigned &DestReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const { + SrcSubIdx = DstSubIdx = 0; // No sub-registers. if (MI.getOpcode() == PIC16::copy_fsr || MI.getOpcode() == PIC16::copy_w) { diff --git a/lib/Target/PIC16/PIC16InstrInfo.h b/lib/Target/PIC16/PIC16InstrInfo.h index 98475db..04927b7 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.h +++ b/lib/Target/PIC16/PIC16InstrInfo.h @@ -61,8 +61,8 @@ public: const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const; virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, - unsigned &DestReg) const; + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; }; diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index e2faf40..f0eabde 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -42,7 +42,11 @@ const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const { bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, - unsigned& destReg) const { + unsigned& destReg, + unsigned& sourceSubIdx, + unsigned& destSubIdx) const { + sourceSubIdx = destSubIdx = 0; // No sub-registers. + unsigned oc = MI.getOpcode(); if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index f45b5ef..7b831cf 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -86,12 +86,11 @@ public: /// This is used for addressing modes. virtual const TargetRegisterClass *getPointerRegClass() const; - // Return true if the instruction is a register to register move and - // leave the source and dest operands in the passed parameters. - // - virtual bool isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg) const; + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. + virtual bool isMoveInstr(const MachineInstr &MI, + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 8601cbe..a6cee0e 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -33,7 +33,10 @@ static bool isZeroImm(const MachineOperand &op) { /// leave the source and dest operands in the passed parameters. /// bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg) const { + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSR, unsigned &DstSR) const { + SrcSR = DstSR = 0; // No sub-registers. + // We look for 3 kinds of patterns here: // or with G0 or 0 // add with G0 or 0 diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index 68a6de3..ab661b9 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -43,11 +43,11 @@ public: /// virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and - /// leave the source and dest operands in the passed parameters. - /// + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg) const; + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 3a05c8a..f657d37 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -783,9 +783,9 @@ bool X86FastISel::X86SelectBranch(Instruction *I) { const MachineInstr &MI = *RI; if (MI.modifiesRegister(Reg)) { - unsigned Src, Dst; + unsigned Src, Dst, SrcSR, DstSR; - if (getInstrInfo()->isMoveInstr(MI, Src, Dst)) { + if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) { Reg = Src; continue; } diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index c4d9798..188d402 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -663,8 +663,8 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) } bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg) const { + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const { switch (MI.getOpcode()) { default: return false; @@ -697,8 +697,10 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, MI.getOperand(0).isReg() && MI.getOperand(1).isReg() && "invalid register-register move instruction"); - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); + SrcReg = MI.getOperand(1).getReg(); + DstReg = MI.getOperand(0).getReg(); + SrcSubIdx = MI.getOperand(1).getSubReg(); + DstSubIdx = MI.getOperand(0).getSubReg(); return true; } } diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index b9cd961..077de56 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -285,11 +285,12 @@ public: /// virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } - // Return true if the instruction is a register to register move and - // leave the source and dest operands in the passed parameters. - // - bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, - unsigned& destReg) const; + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. + virtual bool isMoveInstr(const MachineInstr &MI, + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; + unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp index 53acd60..f966d85 100644 --- a/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -402,8 +402,8 @@ void XCoreAsmPrinter::printMachineInstruction(const MachineInstr *MI) { ++EmittedInsts; // Check for mov mnemonic - unsigned src, dst; - if (TM.getInstrInfo()->isMoveInstr(*MI, src, dst)) { + unsigned src, dst, srcSR, dstSR; + if (TM.getInstrInfo()->isMoveInstr(*MI, src, dst, srcSR, dstSR)) { O << "\tmov "; O << TM.getRegisterInfo()->get(dst).AsmName; O << ", "; diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 545a285..1a16fe0 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -49,7 +49,10 @@ static bool isZeroImm(const MachineOperand &op) { /// leave the source and dest operands in the passed parameters. /// bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg) const { + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSR, unsigned &DstSR) const { + SrcSR = DstSR = 0; // No sub-registers. + // We look for 4 kinds of patterns here: // add dst, src, 0 // sub dst, src, 0 diff --git a/lib/Target/XCore/XCoreInstrInfo.h b/lib/Target/XCore/XCoreInstrInfo.h index 6a246b4..a2c1e67 100644 --- a/lib/Target/XCore/XCoreInstrInfo.h +++ b/lib/Target/XCore/XCoreInstrInfo.h @@ -30,11 +30,11 @@ public: /// virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and - /// leave the source and dest operands in the passed parameters. - /// + /// Return true if the instruction is a register to register move and return + /// the source and dest operands and their sub-register indices by reference. virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg) const; + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of |