diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 5 | ||||
| -rw-r--r-- | test/CodeGen/X86/split-vector-rem.ll | 15 |
2 files changed, 19 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 4ddcbf6..c6b4662 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -6341,7 +6341,10 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, case ISD::FPOW: case ISD::AND: case ISD::OR: - case ISD::XOR: { + case ISD::XOR: + case ISD::UREM: + case ISD::SREM: + case ISD::FREM: { SDOperand LL, LH, RL, RH; SplitVectorOp(Node->getOperand(0), LL, LH); SplitVectorOp(Node->getOperand(1), RL, RH); diff --git a/test/CodeGen/X86/split-vector-rem.ll b/test/CodeGen/X86/split-vector-rem.ll new file mode 100644 index 0000000..8c88769 --- /dev/null +++ b/test/CodeGen/X86/split-vector-rem.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86-64 | grep div | count 16 +; RUN: llvm-as < %s | llc -march=x86-64 | grep fmodf | count 8 + +define <8 x i32> @foo(<8 x i32> %t, <8 x i32> %u) { + %m = srem <8 x i32> %t, %u + ret <8 x i32> %m +} +define <8 x i32> @bar(<8 x i32> %t, <8 x i32> %u) { + %m = urem <8 x i32> %t, %u + ret <8 x i32> %m +} +define <8 x float> @qux(<8 x float> %t, <8 x float> %u) { + %m = frem <8 x float> %t, %u + ret <8 x float> %m +} |