diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 54 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 46 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 135 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 5 | ||||
| -rw-r--r-- | test/MC/ARM/load-store-acquire-release-v8-thumb.s | 33 | ||||
| -rw-r--r-- | test/MC/ARM/load-store-acquire-release-v8.s | 33 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/load-store-acquire-release-v8-thumb.txt | 33 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/load-store-acquire-release-v8.txt | 32 |
9 files changed, 349 insertions, 27 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 6d4de3d..e505e1a 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -500,8 +500,7 @@ class JTI<dag oops, dag iops, InstrItinClass itin, : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin, asm, "", pattern>; -// Atomic load/store instructions -class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, +class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, opc, asm, "", pattern> { @@ -512,23 +511,52 @@ class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, let Inst{20} = 1; let Inst{19-16} = addr; let Inst{15-12} = Rt; - let Inst{11-0} = 0b111110011111; + let Inst{11-10} = 0b11; + let Inst{9-8} = opcod2; + let Inst{7-0} = 0b10011111; } -class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, +class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, opc, asm, "", pattern> { - bits<4> Rd; bits<4> Rt; bits<4> addr; let Inst{27-23} = 0b00011; let Inst{22-21} = opcod; let Inst{20} = 0; let Inst{19-16} = addr; - let Inst{15-12} = Rd; - let Inst{11-4} = 0b11111001; + let Inst{11-10} = 0b11; + let Inst{9-8} = opcod2; + let Inst{7-4} = 0b1001; let Inst{3-0} = Rt; } +// Atomic load/store instructions +class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, + string opc, string asm, list<dag> pattern> + : AIldr_ex_or_acq<opcod, 0b11, oops, iops, itin, opc, asm, pattern>; + +class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, + string opc, string asm, list<dag> pattern> + : AIstr_ex_or_rel<opcod, 0b11, oops, iops, itin, opc, asm, pattern> { + bits<4> Rd; + let Inst{15-12} = Rd; +} + +// Exclusive load/store instructions + +class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, + string opc, string asm, list<dag> pattern> + : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, + Requires<[IsARM, HasV8]>; + +class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, + string opc, string asm, list<dag> pattern> + : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, + Requires<[IsARM, HasV8]> { + bits<4> Rd; + let Inst{15-12} = Rd; +} + class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> { bits<4> Rt; @@ -545,6 +573,18 @@ class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> let Unpredictable{11-8} = 0b1111; let DecoderMethod = "DecodeSwap"; } +// Acquire/Release load/store instructions +class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, + string opc, string asm, list<dag> pattern> + : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, + Requires<[IsARM, HasV8]>; + +class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, + string opc, string asm, list<dag> pattern> + : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, + Requires<[IsARM, HasV8]> { + let Inst{15-12} = 0b1111; +} // addrmode1 instructions class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index dc9a6d2..201b640 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2295,6 +2295,13 @@ def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2), []>, Requires<[IsARM, HasV5TE]>; } +def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), + NoItinerary, "lda", "\t$Rt, $addr", []>; +def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), + NoItinerary, "ldab", "\t$Rt, $addr", []>; +def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), + NoItinerary, "ldah", "\t$Rt, $addr", []>; + // Indexed loads multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass iii, InstrItinClass iir> { @@ -2837,6 +2844,12 @@ multiclass AI3strT<bits<4> op, string opc> { defm STRHT : AI3strT<0b1011, "strht">; +def STL : AIstrrel<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), + NoItinerary, "stl", "\t$Rt, $addr", []>; +def STLB : AIstrrel<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), + NoItinerary, "stlb", "\t$Rt, $addr", []>; +def STLH : AIstrrel<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), + NoItinerary, "stlh", "\t$Rt, $addr", []>; //===----------------------------------------------------------------------===// // Load / store multiple Instructions. @@ -4423,8 +4436,7 @@ def strex_4 : PatFrag<(ops node:$val, node:$ptr), let mayLoad = 1 in { def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), - NoItinerary, - "ldrexb", "\t$Rt, $addr", + NoItinerary, "ldrexb", "\t$Rt, $addr", [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldrexh", "\t$Rt, $addr", @@ -4433,10 +4445,22 @@ def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldrex", "\t$Rt, $addr", [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; let hasExtraDefRegAllocReq = 1 in -def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), +def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), NoItinerary, "ldrexd", "\t$Rt, $addr", []> { let DecoderMethod = "DecodeDoubleRegLoad"; } + +def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), + NoItinerary, "ldaexb", "\t$Rt, $addr", []>; +def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), + NoItinerary, "ldaexh", "\t$Rt, $addr", []>; +def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), + NoItinerary, "ldaex", "\t$Rt, $addr", []>; +let hasExtraDefRegAllocReq = 1 in +def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), + NoItinerary, "ldaexd", "\t$Rt, $addr", []> { + let DecoderMethod = "DecodeDoubleRegLoad"; +} } let mayStore = 1, Constraints = "@earlyclobber $Rd" in { @@ -4455,8 +4479,22 @@ def STREXD : AIstrex<0b01, (outs GPR:$Rd), NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { let DecoderMethod = "DecodeDoubleRegStore"; } +def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), + NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", + []>; +def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), + NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", + []>; +def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), + NoItinerary, "stlex", "\t$Rd, $Rt, $addr", + []>; +let hasExtraSrcRegAllocReq = 1 in +def STLEXD : AIstlex<0b01, (outs GPR:$Rd), + (ins GPRPairOp:$Rt, addr_offset_none:$addr), + NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { + let DecoderMethod = "DecodeDoubleRegStore"; +} } - def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", [(int_arm_clrex)]>, diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index f3464cc..c8c9c9b 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1396,6 +1396,28 @@ def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>; def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>; def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>; +class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops, string opc, string asm, list<dag> pattern> + : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc, asm, "", pattern> { + bits<4> Rt; + bits<4> addr; + + let Inst{31-27} = 0b11101; + let Inst{26-24} = 0b000; + let Inst{23-20} = bits23_20; + let Inst{11-6} = 0b111110; + let Inst{5-4} = bit54; + let Inst{3-0} = 0b1111; + + // Encode instruction operands + let Inst{19-16} = addr; + let Inst{15-12} = Rt; +} + +def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt), (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>; +def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>; +def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>; + + // Store defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, BinOpFrag<(store node:$LHS, node:$RHS)>>; @@ -1539,6 +1561,29 @@ def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb), IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm", "$addr.base = $wb", []>; +class T2Istrrel<bits<2> bit54, dag oops, dag iops, string opc, string asm, list<dag> pattern> + : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc, asm, "", pattern> { + bits<4> Rt; + bits<4> addr; + + let Inst{31-27} = 0b11101; + let Inst{26-20} = 0b0001100; + let Inst{11-6} = 0b111110; + let Inst{5-4} = bit54; + let Inst{3-0} = 0b1111; + + // Encode instruction operands + let Inst{19-16} = addr; + let Inst{15-12} = Rt; +} + +def t2STL : T2Istrrel<0b10, (outs rGPR:$Rt), (ins addr_offset_none:$addr), + "stl", "\t$Rt, $addr", []>; +def t2STLB : T2Istrrel<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr), + "stlb", "\t$Rt, $addr", []>; +def t2STLH : T2Istrrel<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr), + "stlh", "\t$Rt, $addr", []>; + // T2Ipl (Preload Data/Instruction) signals the memory system of possible future // data/instruction access. // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0), @@ -3126,15 +3171,14 @@ def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary, let Inst{3-0} = opt; } -class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, +class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz, InstrItinClass itin, string opc, string asm, string cstr, list<dag> pattern, bits<4> rt2 = 0b1111> : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { let Inst{31-27} = 0b11101; let Inst{26-20} = 0b0001101; let Inst{11-8} = rt2; - let Inst{7-6} = 0b01; - let Inst{5-4} = opcod; + let Inst{7-4} = opcod; let Inst{3-0} = 0b1111; bits<4> addr; @@ -3142,15 +3186,14 @@ class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, let Inst{19-16} = addr; let Inst{15-12} = Rt; } -class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, +class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz, InstrItinClass itin, string opc, string asm, string cstr, list<dag> pattern, bits<4> rt2 = 0b1111> : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { let Inst{31-27} = 0b11101; let Inst{26-20} = 0b0001100; let Inst{11-8} = rt2; - let Inst{7-6} = 0b01; - let Inst{5-4} = opcod; + let Inst{7-4} = opcod; bits<4> Rd; bits<4> addr; @@ -3161,11 +3204,11 @@ class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, } let mayLoad = 1 in { -def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr), +def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr), AddrModeNone, 4, NoItinerary, "ldrexb", "\t$Rt, $addr", "", [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; -def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr), +def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr), AddrModeNone, 4, NoItinerary, "ldrexh", "\t$Rt, $addr", "", [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; @@ -3183,7 +3226,7 @@ def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr), let Inst{7-0} = addr{7-0}; } let hasExtraDefRegAllocReq = 1 in -def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), +def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2), (ins addr_offset_none:$addr), AddrModeNone, 4, NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", "", @@ -3191,16 +3234,48 @@ def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), bits<4> Rt2; let Inst{11-8} = Rt2; } +def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr), + AddrModeNone, 4, NoItinerary, + "ldaexb", "\t$Rt, $addr", "", + []>, Requires<[IsThumb, HasV8]>; +def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr), + AddrModeNone, 4, NoItinerary, + "ldaexh", "\t$Rt, $addr", "", + []>, Requires<[IsThumb, HasV8]>; +def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr), + AddrModeNone, 4, NoItinerary, + "ldaex", "\t$Rt, $addr", "", + []>, Requires<[IsThumb, HasV8]> { + bits<4> Rt; + bits<4> addr; + let Inst{31-27} = 0b11101; + let Inst{26-20} = 0b0001101; + let Inst{19-16} = addr; + let Inst{15-12} = Rt; + let Inst{11-8} = 0b1111; + let Inst{7-0} = 0b11101111; +} +let hasExtraDefRegAllocReq = 1 in +def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2), + (ins addr_offset_none:$addr), + AddrModeNone, 4, NoItinerary, + "ldaexd", "\t$Rt, $Rt2, $addr", "", + [], {?, ?, ?, ?}>, Requires<[HasV8]> { + bits<4> Rt2; + let Inst{11-8} = Rt2; + + let Inst{7} = 1; +} } let mayStore = 1, Constraints = "@earlyclobber $Rd" in { -def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), +def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd), (ins rGPR:$Rt, addr_offset_none:$addr), AddrModeNone, 4, NoItinerary, "strexb", "\t$Rd, $Rt, $addr", "", [(set rGPR:$Rd, (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>; -def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), +def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd), (ins rGPR:$Rt, addr_offset_none:$addr), AddrModeNone, 4, NoItinerary, "strexh", "\t$Rd, $Rt, $addr", "", @@ -3224,7 +3299,7 @@ def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, let Inst{7-0} = addr{7-0}; } let hasExtraSrcRegAllocReq = 1 in -def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd), +def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), AddrModeNone, 4, NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], @@ -3232,6 +3307,42 @@ def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd), bits<4> Rt2; let Inst{11-8} = Rt2; } +def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd), + (ins rGPR:$Rt, addr_offset_none:$addr), + AddrModeNone, 4, NoItinerary, + "stlexb", "\t$Rd, $Rt, $addr", "", + []>, Requires<[IsThumb, HasV8]>; + +def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd), + (ins rGPR:$Rt, addr_offset_none:$addr), + AddrModeNone, 4, NoItinerary, + "stlexh", "\t$Rd, $Rt, $addr", "", + []>, Requires<[IsThumb, HasV8]>; + +def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, + addr_offset_none:$addr), + AddrModeNone, 4, NoItinerary, + "stlex", "\t$Rd, $Rt, $addr", "", + []>, Requires<[IsThumb, HasV8]> { + bits<4> Rd; + bits<4> Rt; + bits<4> addr; + let Inst{31-27} = 0b11101; + let Inst{26-20} = 0b0001100; + let Inst{19-16} = addr; + let Inst{15-12} = Rt; + let Inst{11-4} = 0b11111110; + let Inst{3-0} = Rd; +} +let hasExtraSrcRegAllocReq = 1 in +def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd), + (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), + AddrModeNone, 4, NoItinerary, + "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], + {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> { + bits<4> Rt2; + let Inst{11-8} = Rt2; +} } def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>, diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 7467071..b0037f0 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5201,8 +5201,9 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // expressed as a GPRPair, so we have to manually merge them. // FIXME: We would really like to be able to tablegen'erate this. if (!isThumb() && Operands.size() > 4 && - (Mnemonic == "ldrexd" || Mnemonic == "strexd")) { - bool isLoad = (Mnemonic == "ldrexd"); + (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || + Mnemonic == "stlexd")) { + bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); unsigned Idx = isLoad ? 2 : 3; ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]); ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]); diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 97da232..8b99c17 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -249,9 +249,10 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, // GPRs. However, when decoding them, the two GRPs cannot be automatically // expressed as a GPRPair, so we have to manually merge them. // FIXME: We would really like to be able to tablegen'erate this. - if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD) { + if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD || + Opcode == ARM::LDAEXD || Opcode == ARM::STLEXD) { const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID); - bool isStore = Opcode == ARM::STREXD; + bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD; unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); if (MRC.contains(Reg)) { MCInst NewMI; diff --git a/test/MC/ARM/load-store-acquire-release-v8-thumb.s b/test/MC/ARM/load-store-acquire-release-v8-thumb.s new file mode 100644 index 0000000..fe45757 --- /dev/null +++ b/test/MC/ARM/load-store-acquire-release-v8-thumb.s @@ -0,0 +1,33 @@ +@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s + ldaexb r3, [r4] + ldaexh r2, [r5] + ldaex r1, [r7] + ldaexd r6, r7, [r8] + +@ CHECK: ldaexb r3, [r4] @ encoding: [0xd4,0xe8,0xcf,0x3f] +@ CHECK: ldaexh r2, [r5] @ encoding: [0xd5,0xe8,0xdf,0x2f] +@ CHECK: ldaex r1, [r7] @ encoding: [0xd7,0xe8,0xef,0x1f] +@ CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67] + + stlexb r1, r3, [r4] + stlexh r4, r2, [r5] + stlex r2, r1, [r7] + stlexd r6, r2, r3, [r8] +@ CHECK: stlexb r1, r3, [r4] @ encoding: [0xc4,0xe8,0xc1,0x3f] +@ CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f] +@ CHECK: stlex r2, r1, [r7] @ encoding: [0xc7,0xe8,0xe2,0x1f] +@ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0xc8,0xe8,0xf6,0x23] + + lda r5, [r6] + ldab r5, [r6] + ldah r12, [r9] +@ CHECK: lda r5, [r6] @ encoding: [0xd6,0xe8,0xaf,0x5f] +@ CHECK: ldab r5, [r6] @ encoding: [0xd6,0xe8,0x8f,0x5f] +@ CHECK: ldah r12, [r9] @ encoding: [0xd9,0xe8,0x9f,0xcf] + + stl r3, [r0] + stlb r2, [r1] + stlh r2, [r3] +@ CHECK: stl r3, [r0] @ encoding: [0xc0,0xe8,0xaf,0x3f] +@ CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f] +@ CHECK: stlh r2, [r3] @ encoding: [0xc3,0xe8,0x9f,0x2f] diff --git a/test/MC/ARM/load-store-acquire-release-v8.s b/test/MC/ARM/load-store-acquire-release-v8.s new file mode 100644 index 0000000..85f8306 --- /dev/null +++ b/test/MC/ARM/load-store-acquire-release-v8.s @@ -0,0 +1,33 @@ +@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s + ldaexb r3, [r4] + ldaexh r2, [r5] + ldaex r1, [r7] + ldaexd r6, r7, [r8] + +@ CHECK: ldaexb r3, [r4] @ encoding: [0x9f,0x3e,0xd4,0xe1] +@ CHECK: ldaexh r2, [r5] @ encoding: [0x9f,0x2e,0xf5,0xe1] +@ CHECK: ldaex r1, [r7] @ encoding: [0x9f,0x1e,0x97,0xe1] +@ CHECK: ldaexd r6, r7, [r8] @ encoding: [0x9f,0x6e,0xb8,0xe1] + + stlexb r1, r3, [r4] + stlexh r4, r2, [r5] + stlex r2, r1, [r7] + stlexd r6, r2, r3, [r8] +@ CHECK: stlexb r1, r3, [r4] @ encoding: [0x93,0x1e,0xc4,0xe1] +@ CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1] +@ CHECK: stlex r2, r1, [r7] @ encoding: [0x91,0x2e,0x87,0xe1] +@ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0x92,0x6e,0xa8,0xe1] + + lda r5, [r6] + ldab r5, [r6] + ldah r12, [r9] +@ CHECK: lda r5, [r6] @ encoding: [0x9f,0x5c,0x96,0xe1] +@ CHECK: ldab r5, [r6] @ encoding: [0x9f,0x5c,0xd6,0xe1] +@ CHECK: ldah r12, [r9] @ encoding: [0x9f,0xcc,0xf9,0xe1] + + stl r3, [r0] + stlb r2, [r1] + stlh r2, [r3] +@ CHECK: stl r3, [r0] @ encoding: [0x93,0xfc,0x80,0xe1] +@ CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1] +@ CHECK: stlh r2, [r3] @ encoding: [0x92,0xfc,0xe3,0xe1] diff --git a/test/MC/Disassembler/ARM/load-store-acquire-release-v8-thumb.txt b/test/MC/Disassembler/ARM/load-store-acquire-release-v8-thumb.txt new file mode 100644 index 0000000..8a2ba74 --- /dev/null +++ b/test/MC/Disassembler/ARM/load-store-acquire-release-v8-thumb.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc -triple=thumbv8 -disassemble -show-encoding < %s | FileCheck %s + +0xd4 0xe8 0xcf 0x3f +0xd5 0xe8 0xdf 0x2f +0xd7 0xe8 0xef 0x1f +0xd8 0xe8 0xff 0x67 +# CHECK: ldaexb r3, [r4] @ encoding: [0xd4,0xe8,0xcf,0x3f] +# CHECK: ldaexh r2, [r5] @ encoding: [0xd5,0xe8,0xdf,0x2f] +# CHECK: ldaex r1, [r7] @ encoding: [0xd7,0xe8,0xef,0x1f] +# CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67] + +0xc4 0xe8 0xc1 0x3f +0xc5 0xe8 0xd4 0x2f +0xc7 0xe8 0xe2 0x1f +0xc8 0xe8 0xf6 0x23 +# CHECK: stlexb r1, r3, [r4] @ encoding: [0xc4,0xe8,0xc1,0x3f] +# CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f] +# CHECK: stlex r2, r1, [r7] @ encoding: [0xc7,0xe8,0xe2,0x1f] +# CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0xc8,0xe8,0xf6,0x23] + +0xd6 0xe8 0xaf 0x5f +0xd6 0xe8 0x8f 0x5f +0xd9 0xe8 0x9f 0xcf +# CHECK: lda r5, [r6] @ encoding: [0xd6,0xe8,0xaf,0x5f] +# CHECK: ldab r5, [r6] @ encoding: [0xd6,0xe8,0x8f,0x5f] +# CHECK: ldah r12, [r9] @ encoding: [0xd9,0xe8,0x9f,0xcf] + +0xc0 0xe8 0xaf 0x3f +0xc1 0xe8 0x8f 0x2f +0xc3 0xe8 0x9f 0x2f +# CHECK: stl r3, [r0] @ encoding: [0xc0,0xe8,0xaf,0x3f] +# CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f] +# CHECK: stlh r2, [r3] @ encoding: [0xc3,0xe8,0x9f,0x2f] diff --git a/test/MC/Disassembler/ARM/load-store-acquire-release-v8.txt b/test/MC/Disassembler/ARM/load-store-acquire-release-v8.txt new file mode 100644 index 0000000..058f9cc --- /dev/null +++ b/test/MC/Disassembler/ARM/load-store-acquire-release-v8.txt @@ -0,0 +1,32 @@ +# RUN: llvm-mc -triple=armv8 -disassemble -show-encoding < %s | FileCheck %s +0x9f 0x0e 0xd8 0xe1 +0x9f 0x1e 0xfc 0xe1 +0x9f 0x1e 0x90 0xe1 +0x9f 0x8e 0xbd 0xe1 +# CHECK: ldaexb r0, [r8] @ encoding: [0x9f,0x0e,0xd8,0xe1] +# CHECK: ldaexh r1, [r12] @ encoding: [0x9f,0x1e,0xfc,0xe1] +# CHECK: ldaex r1, [r0] @ encoding: [0x9f,0x1e,0x90,0xe1] +# CHECK: ldaexd r8, r9, [sp] @ encoding: [0x9f,0x8e,0xbd,0xe1] + +0x93 0x1e 0xc4 0xe1 +0x92 0x4e 0xe5 0xe1 +0x91 0x2e 0x87 0xe1 +0x92 0x6e 0xa8 0xe1 +# CHECK: stlexb r1, r3, [r4] @ encoding: [0x93,0x1e,0xc4,0xe1] +# CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1] +# CHECK: stlex r2, r1, [r7] @ encoding: [0x91,0x2e,0x87,0xe1] +# CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0x92,0x6e,0xa8,0xe1] + +0x9f 0x5c 0x96 0xe1 +0x9f 0x5c 0xd6 0xe1 +0x9f 0xcc 0xf9 0xe1 +# CHECK: lda r5, [r6] @ encoding: [0x9f,0x5c,0x96,0xe1] +# CHECK: ldab r5, [r6] @ encoding: [0x9f,0x5c,0xd6,0xe1] +# CHECK: ldah r12, [r9] @ encoding: [0x9f,0xcc,0xf9,0xe1] + +0x93 0xfc 0x80 0xe1 +0x92 0xfc 0xc1 0xe1 +0x92 0xfc 0xe3 0xe1 +# CHECK: stl r3, [r0] @ encoding: [0x93,0xfc,0x80,0xe1] +# CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1] +# CHECK: stlh r2, [r3] @ encoding: [0x92,0xfc,0xe3,0xe1] |