diff options
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 8 | ||||
| -rw-r--r-- | lib/CodeGen/PreAllocSplitting.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.h | 4 | ||||
| -rw-r--r-- | test/CodeGen/X86/pre-split7.ll | 34 |
6 files changed, 60 insertions, 1 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 2fdcf8b..a37e9e6 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -407,6 +407,13 @@ public: return false; } + /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation + /// live interval splitting pass should ignore barriers of the specified + /// register class. + virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{ + return true; + } + /// getPointerRegClass - Returns a TargetRegisterClass used for pointer /// values. virtual const TargetRegisterClass *getPointerRegClass() const { @@ -425,7 +432,6 @@ public: /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction. /// virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; - }; /// TargetInstrInfoImpl - This is the default implementation of diff --git a/lib/CodeGen/PreAllocSplitting.cpp b/lib/CodeGen/PreAllocSplitting.cpp index 547c528..33e3e80 100644 --- a/lib/CodeGen/PreAllocSplitting.cpp +++ b/lib/CodeGen/PreAllocSplitting.cpp @@ -659,6 +659,8 @@ PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs) { // by the current barrier. SmallVector<LiveInterval*, 8> Intervals; for (const TargetRegisterClass **RC = RCs; *RC; ++RC) { + if (TII->IgnoreRegisterClassBarriers(*RC)) + continue; std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC); for (unsigned i = 0, e = VRs.size(); i != e; ++i) { unsigned Reg = VRs[i]; diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 04f10c0..c08fdd8 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2411,6 +2411,14 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { return false; } +bool X86InstrInfo:: +IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const { + // FIXME: Ignore bariers of x87 stack registers for now. We can't + // allow any loads of these registers before FpGet_ST0_80. + return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || + RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass; +} + const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); if (Subtarget->is64Bit()) diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 17be894..dc76f3e 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -405,6 +405,11 @@ public: virtual bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; + /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation + /// live interval splitting pass should ignore barriers of the specified + /// register class. + bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const; + const TargetRegisterClass *getPointerRegClass() const; // getBaseOpcodeFor - This function returns the "base" X86 opcode for the diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 93e8613..25d7b07 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -94,6 +94,10 @@ public: /// Code Generation virtual methods... /// + + /// getCrossCopyRegClass - Returns a legal register class to copy a register + /// in the specified class to or from. Returns NULL if it is possible to copy + /// between a two registers of the specified class. const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const; diff --git a/test/CodeGen/X86/pre-split7.ll b/test/CodeGen/X86/pre-split7.ll new file mode 100644 index 0000000..7f7b933 --- /dev/null +++ b/test/CodeGen/X86/pre-split7.ll @@ -0,0 +1,34 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split + +@object_distance = external global double, align 8 ; <double*> [#uses=1] +@axis_slope_angle = external global double, align 8 ; <double*> [#uses=1] +@current_surfaces.b = external global i1 ; <i1*> [#uses=1] + +declare double @sin(double) nounwind readonly + +declare double @asin(double) nounwind readonly + +declare double @tan(double) nounwind readonly + +define fastcc void @trace_line(i32 %line) nounwind { +entry: + %.b3 = load i1* @current_surfaces.b ; <i1> [#uses=1] + br i1 %.b3, label %bb, label %return + +bb: ; preds = %bb, %entry + %0 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=1] + %1 = add double 0.000000e+00, %0 ; <double> [#uses=2] + %2 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=1] + %3 = sub double %1, %2 ; <double> [#uses=2] + store double %3, double* @axis_slope_angle, align 8 + %4 = fdiv double %1, 2.000000e+00 ; <double> [#uses=1] + %5 = tail call double @sin(double %4) nounwind readonly ; <double> [#uses=1] + %6 = mul double 0.000000e+00, %5 ; <double> [#uses=1] + %7 = tail call double @tan(double %3) nounwind readonly ; <double> [#uses=0] + %8 = add double 0.000000e+00, %6 ; <double> [#uses=1] + store double %8, double* @object_distance, align 8 + br label %bb + +return: ; preds = %entry + ret void +} |