diff options
| -rw-r--r-- | lib/Target/ARM/ARMConstantIslandPass.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/Thumb1InstrInfo.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/Thumb1RegisterInfo.cpp | 1 | ||||
| -rw-r--r-- | test/CodeGen/Thumb/pop.ll | 13 |
4 files changed, 19 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index c44ea2e..43a823d 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -1359,9 +1359,11 @@ bool ARMConstantIslands::UndoLRSpillRestore() { bool MadeChange = false; for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) { MachineInstr *MI = PushPopMIs[i]; + // First two operands are predicates, the third is a zero since there + // is no writeback. if (MI->getOpcode() == ARM::tPOP_RET && - MI->getOperand(2).getReg() == ARM::PC && - MI->getNumExplicitOperands() == 3) { + MI->getOperand(3).getReg() == ARM::PC && + MI->getNumExplicitOperands() == 4) { BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET)); MI->eraseFromParent(); MadeChange = true; diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp index dc4ce64..e1f9338 100644 --- a/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -178,6 +178,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB, DebugLoc DL = MI->getDebugLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP)); AddDefaultPred(MIB); + MIB.addReg(0); // No write back. bool NumRegs = 0; for (unsigned i = CSI.size(); i != 0; --i) { diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index ea5f072..0cea27f 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -863,6 +863,7 @@ void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF, // Epilogue for vararg functions: pop LR to R3 and branch off it. // FIXME: Verify this is still ok when R3 is no longer being reserved. AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) + .addReg(0) // No write back. .addReg(ARM::R3, RegState::Define); emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize); diff --git a/test/CodeGen/Thumb/pop.ll b/test/CodeGen/Thumb/pop.ll new file mode 100644 index 0000000..c5e86ad --- /dev/null +++ b/test/CodeGen/Thumb/pop.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s +; rdar://7268481 + +define arm_apcscc void @t(i8* %a, ...) nounwind { +; CHECK: t: +; CHECK: pop {r3} +; CHECK-NEXT: add sp, #3 * 4 +; CHECK-NEXT: bx r3 +entry: + %a.addr = alloca i8* + store i8* %a, i8** %a.addr + ret void +} |