diff options
| -rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 7 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcInstr64Bit.td | 2 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/64bit.ll | 23 |
3 files changed, 32 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index d0156fa..e09802b 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -1397,6 +1397,13 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setOperationAction(ISD::SETCC, MVT::i64, Expand); setOperationAction(ISD::BR_CC, MVT::i64, Custom); setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); + + setOperationAction(ISD::CTPOP, MVT::i64, Legal); + setOperationAction(ISD::CTTZ , MVT::i64, Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); + setOperationAction(ISD::CTLZ , MVT::i64, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); + setOperationAction(ISD::BSWAP, MVT::i64, Expand); } // FIXME: There are instructions available for ATOMIC_FENCE diff --git a/lib/Target/Sparc/SparcInstr64Bit.td b/lib/Target/Sparc/SparcInstr64Bit.td index d44c18d..cf8747d 100644 --- a/lib/Target/Sparc/SparcInstr64Bit.td +++ b/lib/Target/Sparc/SparcInstr64Bit.td @@ -169,6 +169,8 @@ def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>; def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>; +def : Pat<(ctpop i64:$src), (POPCrr $src)>; + } // Predicates = [Is64Bit] diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll index f778f9d..f5ed047 100644 --- a/test/CodeGen/SPARC/64bit.ll +++ b/test/CodeGen/SPARC/64bit.ll @@ -285,3 +285,26 @@ entry: store i64 0, i64* %0, align 8 ret i64 0 } + +; CHECK-LABEL: bit_ops +; CHECK: popc + +; OPT-LABEL: bit_ops +; OPT: popc + +define i64 @bit_ops(i64 %arg) { +entry: + %0 = tail call i64 @llvm.ctpop.i64(i64 %arg) + %1 = tail call i64 @llvm.ctlz.i64(i64 %arg, i1 true) + %2 = tail call i64 @llvm.cttz.i64(i64 %arg, i1 true) + %3 = tail call i64 @llvm.bswap.i64(i64 %arg) + %4 = add i64 %0, %1 + %5 = add i64 %2, %3 + %6 = add i64 %4, %5 + ret i64 %6 +} + +declare i64 @llvm.ctpop.i64(i64) nounwind readnone +declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone +declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone +declare i64 @llvm.bswap.i64(i64) nounwind readnone |