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-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypes.h17
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp30
-rw-r--r--test/CodeGen/X86/2008-07-23-VSetCC.ll30
3 files changed, 68 insertions, 9 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 8122459..644bb10 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -418,6 +418,7 @@ private:
SDOperand ScalarizeVecRes_SELECT(SDNode *N);
SDOperand ScalarizeVecRes_UNDEF(SDNode *N);
SDOperand ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
+ SDOperand ScalarizeVecRes_VSETCC(SDNode *N);
// Vector Operand Scalarization: <1 x ty> -> ty.
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
@@ -434,19 +435,19 @@ private:
// Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
void SplitVectorResult(SDNode *N, unsigned OpNo);
+ void SplitVecRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitVecRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_LOAD(LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_BUILD_PAIR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo, SDOperand &Hi);
-
void SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
- void SplitVecRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
void SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitVecRes_LOAD(LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitVecRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+ void SplitVecRes_VSETCC(SDNode *N, SDOperand &Lo, SDOperand &Hi);
// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
bool SplitVectorOperand(SDNode *N, unsigned OpNo);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 9f6f3e7..f0875fa 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -46,9 +46,10 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
- case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
+ case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
+ case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
case ISD::ADD:
case ISD::FADD:
@@ -141,6 +142,19 @@ SDOperand DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
return GetScalarizedVector(N->getOperand(Op));
}
+SDOperand DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
+ MVT NewVT = N->getValueType(0).getVectorElementType();
+ SDOperand LHS = GetScalarizedVector(N->getOperand(0));
+ SDOperand RHS = GetScalarizedVector(N->getOperand(1));
+ LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS,
+ N->getOperand(2));
+ return
+ DAG.getNode(ISD::SELECT, NewVT, LHS,
+ DAG.getConstant(APInt::getAllOnesValue(NewVT.getSizeInBits()),
+ NewVT),
+ DAG.getConstant(0ULL, NewVT));
+}
+
//===----------------------------------------------------------------------===//
// Operand Vector Scalarization <1 x ty> -> ty.
@@ -251,6 +265,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
+ case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
case ISD::CTTZ:
case ISD::CTLZ:
@@ -520,6 +535,19 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo,
Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
}
+void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDOperand &Lo,
+ SDOperand &Hi) {
+ MVT LoVT, HiVT;
+ GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
+
+ SDOperand LL, LH, RL, RH;
+ GetSplitVector(N->getOperand(0), LL, LH);
+ GetSplitVector(N->getOperand(1), RL, RH);
+
+ Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
+ Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
+}
+
//===----------------------------------------------------------------------===//
// Operand Vector Splitting
diff --git a/test/CodeGen/X86/2008-07-23-VSetCC.ll b/test/CodeGen/X86/2008-07-23-VSetCC.ll
new file mode 100644
index 0000000..735c610
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-23-VSetCC.ll
@@ -0,0 +1,30 @@
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium
+; PR2575
+
+define void @entry(i32 %m_task_id, i32 %start_x, i32 %end_x) nounwind {
+ br i1 false, label %bb.nph, label %._crit_edge
+
+bb.nph: ; preds = %bb.nph, %0
+ vicmp sgt <4 x i32> zeroinitializer, < i32 -128, i32 -128, i32 -128, i32 -128 > ; <<4 x i32>>:1 [#uses=1]
+ extractelement <4 x i32> %1, i32 3 ; <i32>:2 [#uses=1]
+ lshr i32 %2, 31 ; <i32>:3 [#uses=1]
+ trunc i32 %3 to i1 ; <i1>:4 [#uses=1]
+ select i1 %4, i32 -1, i32 0 ; <i32>:5 [#uses=1]
+ insertelement <4 x i32> zeroinitializer, i32 %5, i32 3 ; <<4 x i32>>:6 [#uses=1]
+ and <4 x i32> zeroinitializer, %6 ; <<4 x i32>>:7 [#uses=1]
+ bitcast <4 x i32> %7 to <4 x float> ; <<4 x float>>:8 [#uses=1]
+ mul <4 x float> zeroinitializer, %8 ; <<4 x float>>:9 [#uses=1]
+ bitcast <4 x float> %9 to <4 x i32> ; <<4 x i32>>:10 [#uses=1]
+ or <4 x i32> %10, zeroinitializer ; <<4 x i32>>:11 [#uses=1]
+ bitcast <4 x i32> %11 to <4 x float> ; <<4 x float>>:12 [#uses=1]
+ mul <4 x float> %12, < float 1.000000e+02, float 1.000000e+02, float 1.000000e+02, float 1.000000e+02 > ; <<4 x float>>:13 [#uses=1]
+ sub <4 x float> %13, < float 1.000000e+02, float 1.000000e+02, float 1.000000e+02, float 1.000000e+02 > ; <<4 x float>>:14 [#uses=1]
+ extractelement <4 x float> %14, i32 3 ; <float>:15 [#uses=1]
+ call float @fmaxf( float 0.000000e+00, float %15 ) ; <float>:16 [#uses=0]
+ br label %bb.nph
+
+._crit_edge: ; preds = %0
+ ret void
+}
+
+declare float @fmaxf(float, float)
generated by cgit v1.1 at 2024-10-31 00:45:01 +0000