aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--include/llvm/Target/TargetAsmParser.h3
-rw-r--r--lib/Target/X86/AsmParser/X86AsmParser.cpp291
-rw-r--r--tools/llvm-mc/AsmParser.cpp3
-rw-r--r--tools/llvm-mc/AsmParser.h9
-rw-r--r--tools/llvm-mc/MC-X86Specific.cpp267
-rw-r--r--tools/llvm-mc/llvm-mc.cpp1
6 files changed, 271 insertions, 303 deletions
diff --git a/include/llvm/Target/TargetAsmParser.h b/include/llvm/Target/TargetAsmParser.h
index 5e55693..8b8b210 100644
--- a/include/llvm/Target/TargetAsmParser.h
+++ b/include/llvm/Target/TargetAsmParser.h
@@ -43,8 +43,7 @@ public:
/// \param Name - The instruction name.
/// \param Inst [out] - On success, the parsed instruction.
/// \return True on failure.
- virtual bool ParseInstruction(MCAsmParser &AP, const StringRef &Name,
- MCInst &Inst) = 0;
+ virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst) = 0;
};
} // End llvm namespace
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index aec5e3f..12e9f93 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -9,52 +9,297 @@
#include "X86.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAsmLexer.h"
#include "llvm/MC/MCAsmParser.h"
+#include "llvm/MC/MCValue.h"
+#include "llvm/Support/SourceMgr.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Target/TargetAsmParser.h"
using namespace llvm;
namespace {
- struct X86Operand {
- };
+class X86Operand;
- class X86ATTAsmParser : public TargetAsmParser {
- MCAsmParser &Parser;
+class X86ATTAsmParser : public TargetAsmParser {
+ MCAsmParser &Parser;
- private:
- bool ParseOperand(X86Operand &Op);
-
- bool MatchInstruction(const StringRef &Name,
- llvm::SmallVector<X86Operand, 3> &Operands,
- MCInst &Inst);
+private:
+ bool MatchInstruction(const StringRef &Name,
+ llvm::SmallVector<X86Operand, 3> &Operands,
+ MCInst &Inst);
- MCAsmLexer &getLexer() const { return Parser.getLexer(); }
+ MCAsmParser &getParser() const { return Parser; }
- public:
- X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
- : TargetAsmParser(T), Parser(_Parser) {}
-
- virtual bool ParseInstruction(MCAsmParser &AP, const StringRef &Name,
- MCInst &Inst);
+ MCAsmLexer &getLexer() const { return Parser.getLexer(); }
+
+ void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
+
+ bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
+
+ bool ParseRegister(X86Operand &Op);
+
+ bool ParseOperand(X86Operand &Op);
+
+ bool ParseMemOperand(X86Operand &Op);
+
+public:
+ X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
+ : TargetAsmParser(T), Parser(_Parser) {}
+
+ virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
+};
+
+/// X86Operand - Instances of this class represent a parsed X86 machine
+/// instruction.
+struct X86Operand {
+ enum {
+ Register,
+ Immediate,
+ Memory
+ } Kind;
+
+ union {
+ struct {
+ unsigned RegNo;
+ } Reg;
+
+ struct {
+ MCValue Val;
+ } Imm;
+
+ struct {
+ unsigned SegReg;
+ MCValue Disp;
+ unsigned BaseReg;
+ unsigned IndexReg;
+ unsigned Scale;
+ } Mem;
};
+
+ unsigned getReg() const {
+ assert(Kind == Register && "Invalid access!");
+ return Reg.RegNo;
+ }
+
+ static X86Operand CreateReg(unsigned RegNo) {
+ X86Operand Res;
+ Res.Kind = Register;
+ Res.Reg.RegNo = RegNo;
+ return Res;
+ }
+ static X86Operand CreateImm(MCValue Val) {
+ X86Operand Res;
+ Res.Kind = Immediate;
+ Res.Imm.Val = Val;
+ return Res;
+ }
+ static X86Operand CreateMem(unsigned SegReg, MCValue Disp, unsigned BaseReg,
+ unsigned IndexReg, unsigned Scale) {
+ // If there is no index register, we should never have a scale, and we
+ // should always have a scale (in {1,2,4,8}) if we do.
+ assert(((Scale == 0 && !IndexReg) ||
+ (IndexReg && (Scale == 1 || Scale == 2 ||
+ Scale == 4 || Scale == 8))) &&
+ "Invalid scale!");
+ X86Operand Res;
+ Res.Kind = Memory;
+ Res.Mem.SegReg = SegReg;
+ Res.Mem.Disp = Disp;
+ Res.Mem.BaseReg = BaseReg;
+ Res.Mem.IndexReg = IndexReg;
+ Res.Mem.Scale = Scale;
+ return Res;
+ }
+};
+
+}
+
+//
+
+bool X86ATTAsmParser::ParseRegister(X86Operand &Op) {
+ assert(getLexer().is(AsmToken::Register) && "Invalid token kind!");
+
+ // FIXME: Decode register number.
+ Op = X86Operand::CreateReg(123);
+ getLexer().Lex(); // Eat register token.
+
+ return false;
}
bool X86ATTAsmParser::ParseOperand(X86Operand &Op) {
- return true;
+ switch (getLexer().getKind()) {
+ default:
+ return ParseMemOperand(Op);
+ case AsmToken::Register:
+ // FIXME: if a segment register, this could either be just the seg reg, or
+ // the start of a memory operand.
+ return ParseRegister(Op);
+ case AsmToken::Dollar: {
+ // $42 -> immediate.
+ getLexer().Lex();
+ MCValue Val;
+ if (getParser().ParseRelocatableExpression(Val))
+ return true;
+ Op = X86Operand::CreateImm(Val);
+ return false;
+ }
+ case AsmToken::Star: {
+ getLexer().Lex(); // Eat the star.
+
+ if (getLexer().is(AsmToken::Register)) {
+ if (ParseRegister(Op))
+ return true;
+ } else if (ParseMemOperand(Op))
+ return true;
+
+ // FIXME: Note the '*' in the operand for use by the matcher.
+ return false;
+ }
+ }
+}
+
+/// ParseMemOperand: segment: disp(basereg, indexreg, scale)
+bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
+ // FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
+ unsigned SegReg = 0;
+
+ // We have to disambiguate a parenthesized expression "(4+5)" from the start
+ // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
+ // only way to do this without lookahead is to eat the ( and see what is after
+ // it.
+ MCValue Disp = MCValue::get(0, 0, 0);
+ if (getLexer().isNot(AsmToken::LParen)) {
+ if (getParser().ParseRelocatableExpression(Disp)) return true;
+
+ // After parsing the base expression we could either have a parenthesized
+ // memory address or not. If not, return now. If so, eat the (.
+ if (getLexer().isNot(AsmToken::LParen)) {
+ Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0);
+ return false;
+ }
+
+ // Eat the '('.
+ getLexer().Lex();
+ } else {
+ // Okay, we have a '('. We don't know if this is an expression or not, but
+ // so we have to eat the ( to see beyond it.
+ getLexer().Lex(); // Eat the '('.
+
+ if (getLexer().is(AsmToken::Register) || getLexer().is(AsmToken::Comma)) {
+ // Nothing to do here, fall into the code below with the '(' part of the
+ // memory operand consumed.
+ } else {
+ // It must be an parenthesized expression, parse it now.
+ if (getParser().ParseParenRelocatableExpression(Disp))
+ return true;
+
+ // After parsing the base expression we could either have a parenthesized
+ // memory address or not. If not, return now. If so, eat the (.
+ if (getLexer().isNot(AsmToken::LParen)) {
+ Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0);
+ return false;
+ }
+
+ // Eat the '('.
+ getLexer().Lex();
+ }
+ }
+
+ // If we reached here, then we just ate the ( of the memory operand. Process
+ // the rest of the memory operand.
+ unsigned BaseReg = 0, IndexReg = 0, Scale = 0;
+
+ if (getLexer().is(AsmToken::Register)) {
+ if (ParseRegister(Op))
+ return true;
+ BaseReg = Op.getReg();
+ }
+
+ if (getLexer().is(AsmToken::Comma)) {
+ getLexer().Lex(); // Eat the comma.
+
+ // Following the comma we should have either an index register, or a scale
+ // value. We don't support the later form, but we want to parse it
+ // correctly.
+ //
+ // Not that even though it would be completely consistent to support syntax
+ // like "1(%eax,,1)", the assembler doesn't.
+ if (getLexer().is(AsmToken::Register)) {
+ if (ParseRegister(Op))
+ return true;
+ IndexReg = Op.getReg();
+ Scale = 1; // If not specified, the scale defaults to 1.
+
+ if (getLexer().isNot(AsmToken::RParen)) {
+ // Parse the scale amount:
+ // ::= ',' [scale-expression]
+ if (getLexer().isNot(AsmToken::Comma))
+ return true;
+ getLexer().Lex(); // Eat the comma.
+
+ if (getLexer().isNot(AsmToken::RParen)) {
+ SMLoc Loc = getLexer().getTok().getLoc();
+
+ int64_t ScaleVal;
+ if (getParser().ParseAbsoluteExpression(ScaleVal))
+ return true;
+
+ // Validate the scale amount.
+ if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8)
+ return Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
+ Scale = (unsigned)ScaleVal;
+ }
+ }
+ } else if (getLexer().isNot(AsmToken::RParen)) {
+ // Otherwise we have the unsupported form of a scale amount without an
+ // index.
+ SMLoc Loc = getLexer().getTok().getLoc();
+
+ int64_t Value;
+ if (getParser().ParseAbsoluteExpression(Value))
+ return true;
+
+ return Error(Loc, "cannot have scale factor without index register");
+ }
+ }
+
+ // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
+ if (getLexer().isNot(AsmToken::RParen))
+ return Error(getLexer().getTok().getLoc(),
+ "unexpected token in memory operand");
+ getLexer().Lex(); // Eat the ')'.
+
+ Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale);
+ return false;
}
-bool
-X86ATTAsmParser::MatchInstruction(const StringRef &Name,
+bool
+X86ATTAsmParser::MatchInstruction(const StringRef &Name,
llvm::SmallVector<X86Operand, 3> &Operands,
MCInst &Inst) {
return false;
}
-bool X86ATTAsmParser::ParseInstruction(MCAsmParser &AP, const StringRef &Name,
- MCInst &Inst) {
+bool X86ATTAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
llvm::SmallVector<X86Operand, 3> Operands;
-
+
+ if (getLexer().isNot(AsmToken::EndOfStatement)) {
+ // Read the first operand.
+ Operands.push_back(X86Operand());
+ if (ParseOperand(Operands.back()))
+ return true;
+
+ while (getLexer().is(AsmToken::Comma)) {
+ getLexer().Lex(); // Eat the comma.
+
+ // Parse and remember the operand.
+ Operands.push_back(X86Operand());
+ if (ParseOperand(Operands.back()))
+ return true;
+ }
+ }
+
return MatchInstruction(Name, Operands, Inst);
}
diff --git a/tools/llvm-mc/AsmParser.cpp b/tools/llvm-mc/AsmParser.cpp
index e4c85a7..3cd2b8e 100644
--- a/tools/llvm-mc/AsmParser.cpp
+++ b/tools/llvm-mc/AsmParser.cpp
@@ -551,8 +551,7 @@ bool AsmParser::ParseStatement() {
}
MCInst Inst;
- if (ParseX86InstOperands(IDVal, Inst) &&
- getTargetParser().ParseInstruction(*this, IDVal, Inst))
+ if (getTargetParser().ParseInstruction(IDVal, Inst))
return true;
if (Lexer.isNot(AsmToken::EndOfStatement))
diff --git a/tools/llvm-mc/AsmParser.h b/tools/llvm-mc/AsmParser.h
index e59e85c..2f61461 100644
--- a/tools/llvm-mc/AsmParser.h
+++ b/tools/llvm-mc/AsmParser.h
@@ -28,9 +28,6 @@ class TargetAsmParser;
class Twine;
class AsmParser : public MCAsmParser {
-public:
- struct X86Operand;
-
private:
AsmLexer Lexer;
MCContext &Ctx;
@@ -88,12 +85,6 @@ private:
bool ParseBinOpRHS(unsigned Precedence, AsmExpr *&Res);
bool ParseParenExpr(AsmExpr *&Res);
- // X86 specific.
- bool ParseX86InstOperands(const StringRef &InstName, MCInst &Inst);
- bool ParseX86Operand(X86Operand &Op);
- bool ParseX86MemOperand(X86Operand &Op);
- bool ParseX86Register(X86Operand &Op);
-
// Directive Parsing.
bool ParseDirectiveDarwinSection(); // Darwin specific ".section".
bool ParseDirectiveSectionSwitch(const char *Section,
diff --git a/tools/llvm-mc/MC-X86Specific.cpp b/tools/llvm-mc/MC-X86Specific.cpp
deleted file mode 100644
index 139d485..0000000
--- a/tools/llvm-mc/MC-X86Specific.cpp
+++ /dev/null
@@ -1,267 +0,0 @@
-//===- MC-X86Specific.cpp - X86-Specific code for MC ----------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements X86-specific parsing, encoding and decoding stuff for
-// MC.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AsmParser.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/Support/SourceMgr.h"
-using namespace llvm;
-
-/// X86Operand - Instances of this class represent one X86 machine instruction.
-struct AsmParser::X86Operand {
- enum {
- Register,
- Immediate,
- Memory
- } Kind;
-
- union {
- struct {
- unsigned RegNo;
- } Reg;
-
- struct {
- MCValue Val;
- } Imm;
-
- struct {
- unsigned SegReg;
- MCValue Disp;
- unsigned BaseReg;
- unsigned IndexReg;
- unsigned Scale;
- } Mem;
- };
-
- unsigned getReg() const {
- assert(Kind == Register && "Invalid access!");
- return Reg.RegNo;
- }
-
- static X86Operand CreateReg(unsigned RegNo) {
- X86Operand Res;
- Res.Kind = Register;
- Res.Reg.RegNo = RegNo;
- return Res;
- }
- static X86Operand CreateImm(MCValue Val) {
- X86Operand Res;
- Res.Kind = Immediate;
- Res.Imm.Val = Val;
- return Res;
- }
- static X86Operand CreateMem(unsigned SegReg, MCValue Disp, unsigned BaseReg,
- unsigned IndexReg, unsigned Scale) {
- // If there is no index register, we should never have a scale, and we
- // should always have a scale (in {1,2,4,8}) if we do.
- assert(((Scale == 0 && !IndexReg) ||
- (IndexReg && (Scale == 1 || Scale == 2 ||
- Scale == 4 || Scale == 8))) &&
- "Invalid scale!");
- X86Operand Res;
- Res.Kind = Memory;
- Res.Mem.SegReg = SegReg;
- Res.Mem.Disp = Disp;
- Res.Mem.BaseReg = BaseReg;
- Res.Mem.IndexReg = IndexReg;
- Res.Mem.Scale = Scale;
- return Res;
- }
-};
-
-bool AsmParser::ParseX86Register(X86Operand &Op) {
- assert(getLexer().is(AsmToken::Register) && "Invalid token kind!");
-
- // FIXME: Decode register number.
- Op = X86Operand::CreateReg(123);
- getLexer().Lex(); // Eat register token.
-
- return false;
-}
-
-bool AsmParser::ParseX86Operand(X86Operand &Op) {
- switch (getLexer().getKind()) {
- default:
- return ParseX86MemOperand(Op);
- case AsmToken::Register:
- // FIXME: if a segment register, this could either be just the seg reg, or
- // the start of a memory operand.
- return ParseX86Register(Op);
- case AsmToken::Dollar: {
- // $42 -> immediate.
- getLexer().Lex();
- MCValue Val;
- if (ParseRelocatableExpression(Val))
- return true;
- Op = X86Operand::CreateImm(Val);
- return false;
- }
- case AsmToken::Star: {
- getLexer().Lex(); // Eat the star.
-
- if (getLexer().is(AsmToken::Register)) {
- if (ParseX86Register(Op))
- return true;
- } else if (ParseX86MemOperand(Op))
- return true;
-
- // FIXME: Note the '*' in the operand for use by the matcher.
- return false;
- }
- }
-}
-
-/// ParseX86MemOperand: segment: disp(basereg, indexreg, scale)
-bool AsmParser::ParseX86MemOperand(X86Operand &Op) {
- // FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
- unsigned SegReg = 0;
-
- // We have to disambiguate a parenthesized expression "(4+5)" from the start
- // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
- // only way to do this without lookahead is to eat the ( and see what is after
- // it.
- MCValue Disp = MCValue::get(0, 0, 0);
- if (getLexer().isNot(AsmToken::LParen)) {
- if (ParseRelocatableExpression(Disp)) return true;
-
- // After parsing the base expression we could either have a parenthesized
- // memory address or not. If not, return now. If so, eat the (.
- if (getLexer().isNot(AsmToken::LParen)) {
- Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0);
- return false;
- }
-
- // Eat the '('.
- getLexer().Lex();
- } else {
- // Okay, we have a '('. We don't know if this is an expression or not, but
- // so we have to eat the ( to see beyond it.
- getLexer().Lex(); // Eat the '('.
-
- if (getLexer().is(AsmToken::Register) || getLexer().is(AsmToken::Comma)) {
- // Nothing to do here, fall into the code below with the '(' part of the
- // memory operand consumed.
- } else {
- // It must be an parenthesized expression, parse it now.
- if (ParseParenRelocatableExpression(Disp))
- return true;
-
- // After parsing the base expression we could either have a parenthesized
- // memory address or not. If not, return now. If so, eat the (.
- if (getLexer().isNot(AsmToken::LParen)) {
- Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0);
- return false;
- }
-
- // Eat the '('.
- getLexer().Lex();
- }
- }
-
- // If we reached here, then we just ate the ( of the memory operand. Process
- // the rest of the memory operand.
- unsigned BaseReg = 0, IndexReg = 0, Scale = 0;
-
- if (getLexer().is(AsmToken::Register)) {
- if (ParseX86Register(Op))
- return true;
- BaseReg = Op.getReg();
- }
-
- if (getLexer().is(AsmToken::Comma)) {
- getLexer().Lex(); // Eat the comma.
-
- // Following the comma we should have either an index register, or a scale
- // value. We don't support the later form, but we want to parse it
- // correctly.
- //
- // Not that even though it would be completely consistent to support syntax
- // like "1(%eax,,1)", the assembler doesn't.
- if (getLexer().is(AsmToken::Register)) {
- if (ParseX86Register(Op))
- return true;
- IndexReg = Op.getReg();
- Scale = 1; // If not specified, the scale defaults to 1.
-
- if (getLexer().isNot(AsmToken::RParen)) {
- // Parse the scale amount:
- // ::= ',' [scale-expression]
- if (getLexer().isNot(AsmToken::Comma))
- return true;
- getLexer().Lex(); // Eat the comma.
-
- if (getLexer().isNot(AsmToken::RParen)) {
- int64_t ScaleVal;
- if (ParseAbsoluteExpression(ScaleVal))
- return true;
-
- // Validate the scale amount.
- if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8)
- return TokError("scale factor in address must be 1, 2, 4 or 8");
- Scale = (unsigned)ScaleVal;
- }
- }
- } else if (getLexer().isNot(AsmToken::RParen)) {
- // Otherwise we have the unsupported form of a scale amount without an
- // index.
- SMLoc Loc = getLexer().getTok().getLoc();
-
- int64_t Value;
- if (ParseAbsoluteExpression(Value))
- return true;
-
- return Error(Loc, "cannot have scale factor without index register");
- }
- }
-
- // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
- if (getLexer().isNot(AsmToken::RParen))
- return TokError("unexpected token in memory operand");
- getLexer().Lex(); // Eat the ')'.
-
- Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale);
- return false;
-}
-
-/// MatchX86Inst - Convert a parsed instruction name and operand list into a
-/// concrete instruction.
-static bool MatchX86Inst(const StringRef &Name,
- llvm::SmallVector<AsmParser::X86Operand, 3> &Operands,
- MCInst &Inst) {
- return false;
-}
-
-/// ParseX86InstOperands - Parse the operands of an X86 instruction and return
-/// them as the operands of an MCInst.
-bool AsmParser::ParseX86InstOperands(const StringRef &InstName, MCInst &Inst) {
- llvm::SmallVector<X86Operand, 3> Operands;
-
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- // Read the first operand.
- Operands.push_back(X86Operand());
- if (ParseX86Operand(Operands.back()))
- return true;
-
- while (getLexer().is(AsmToken::Comma)) {
- getLexer().Lex(); // Eat the comma.
-
- // Parse and remember the operand.
- Operands.push_back(X86Operand());
- if (ParseX86Operand(Operands.back()))
- return true;
- }
- }
-
- return MatchX86Inst(InstName, Operands, Inst);
-}
diff --git a/tools/llvm-mc/llvm-mc.cpp b/tools/llvm-mc/llvm-mc.cpp
index e148e35..11d8b96 100644
--- a/tools/llvm-mc/llvm-mc.cpp
+++ b/tools/llvm-mc/llvm-mc.cpp
@@ -196,6 +196,7 @@ static int AssembleInput(const char *ProgName) {
OwningPtr<TargetAsmParser> TAP(GetTargetAsmParser(ProgName, Parser));
if (!TAP)
return 1;
+ Parser.setTargetParser(*TAP.get());
return Parser.Run();
}
generated by cgit v1.1 at 2024-10-31 00:13:30 +0000