diff options
| -rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 13 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 8 | ||||
| -rw-r--r-- | test/MC/Mips/mips-control-instructions.s | 28 | ||||
| -rw-r--r-- | test/MC/Mips/mips_directives.s | 10 |
4 files changed, 49 insertions, 10 deletions
diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index c2a5879..0ae93b4 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -520,6 +520,19 @@ class BRK_FM<bits<6> funct> } //===----------------------------------------------------------------------===// +// Exception return format <Cop0|1|0|funct> +//===----------------------------------------------------------------------===// + +class ER_FM<bits<6> funct> +{ + bits<32> Inst; + let Inst{31-26} = 0x10; + let Inst{25} = 1; + let Inst{24-6} = 0; + let Inst{5-0} = funct; +} + +//===----------------------------------------------------------------------===// // // FLOATING POINT INSTRUCTION FORMATS // diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 1bc1077..6082a3f 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -652,6 +652,11 @@ class BRK_FT<string opstr> : InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; +// (D)Eret +class ER_FT<string opstr> : + InstSE<(outs), (ins), + opstr, [], NoItinerary, FrmOther>; + // Sync let hasSideEffects = 1 in class SYNC_FT : @@ -958,6 +963,9 @@ def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>; def BREAK : BRK_FT<"break">, BRK_FM<0xd>; def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; +def ERET : ER_FT<"eret">, ER_FM<0x18>; +def DERET : ER_FT<"deret">, ER_FM<0x1f>; + /// Load-linked, Store-conditional let Predicates = [NotN64, HasStdEnc] in { def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; diff --git a/test/MC/Mips/mips-control-instructions.s b/test/MC/Mips/mips-control-instructions.s new file mode 100644 index 0000000..ee70940 --- /dev/null +++ b/test/MC/Mips/mips-control-instructions.s @@ -0,0 +1,28 @@ +# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 | \ +# RUN: FileCheck -check-prefix=CHECK32 %s +# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips64r2 | \ +# RUN: FileCheck -check-prefix=CHECK64 %s + +# CHECK32: break # encoding: [0x00,0x00,0x00,0x0d] +# CHECK32: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d] +# CHECK32: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] +# CHECK32: syscall # encoding: [0x00,0x00,0x00,0x0c] +# CHECK32: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] +# CHECK32: eret # encoding: [0x42,0x00,0x00,0x18] +# CHECK32: deret # encoding: [0x42,0x00,0x00,0x1f] + +# CHECK64: break # encoding: [0x00,0x00,0x00,0x0d] +# CHECK64: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d] +# CHECK64: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] +# CHECK64: syscall # encoding: [0x00,0x00,0x00,0x0c] +# CHECK64: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] +# CHECK64: eret # encoding: [0x42,0x00,0x00,0x18] +# CHECK64: deret # encoding: [0x42,0x00,0x00,0x1f] + + break + break 7 + break 7,5 + syscall + syscall 0x3454 + eret + deret diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s index c29806a..bbb2616 100644 --- a/test/MC/Mips/mips_directives.s +++ b/test/MC/Mips/mips_directives.s @@ -41,15 +41,5 @@ $JTI0_0: .set f6,$f6 # CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85] # CHECK: and $3, $15, $15 # encoding: [0x01,0xef,0x18,0x24] -# CHECK: break # encoding: [0x00,0x00,0x00,0x0d] -# CHECK: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d] -# CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] -# CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] -# CHECK: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] abs.s f6,FPU_MASK and r3,$t7,STORE_MASK - break - break 7 - break 7,5 - syscall - syscall 0x3454 |