diff options
| -rw-r--r-- | lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 198 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 75 | ||||
| -rw-r--r-- | test/MC/PowerPC/ppc64-encoding-ext.s | 128 |
3 files changed, 349 insertions, 52 deletions
diff --git a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index d426ba0..2310bb3 100644 --- a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -422,7 +422,8 @@ void PPCOperand::print(raw_ostream &OS) const { void PPCAsmParser:: ProcessInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { - switch (Inst.getOpcode()) { + int Opcode = Inst.getOpcode(); + switch (Opcode) { case PPC::LAx: { MCInst TmpInst; TmpInst.setOpcode(PPC::LA); @@ -472,10 +473,82 @@ ProcessInstruction(MCInst &Inst, Inst = TmpInst; break; } - case PPC::SLWI: { + case PPC::EXTLWI: + case PPC::EXTLWIo: { MCInst TmpInst; int64_t N = Inst.getOperand(2).getImm(); - TmpInst.setOpcode(PPC::RLWINM); + int64_t B = Inst.getOperand(3).getImm(); + TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(B)); + TmpInst.addOperand(MCOperand::CreateImm(0)); + TmpInst.addOperand(MCOperand::CreateImm(N - 1)); + Inst = TmpInst; + break; + } + case PPC::EXTRWI: + case PPC::EXTRWIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + int64_t B = Inst.getOperand(3).getImm(); + TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(B + N)); + TmpInst.addOperand(MCOperand::CreateImm(32 - N)); + TmpInst.addOperand(MCOperand::CreateImm(31)); + Inst = TmpInst; + break; + } + case PPC::INSLWI: + case PPC::INSLWIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + int64_t B = Inst.getOperand(3).getImm(); + TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(32 - B)); + TmpInst.addOperand(MCOperand::CreateImm(B)); + TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); + Inst = TmpInst; + break; + } + case PPC::INSRWI: + case PPC::INSRWIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + int64_t B = Inst.getOperand(3).getImm(); + TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N))); + TmpInst.addOperand(MCOperand::CreateImm(B)); + TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); + Inst = TmpInst; + break; + } + case PPC::ROTRWI: + case PPC::ROTRWIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(32 - N)); + TmpInst.addOperand(MCOperand::CreateImm(0)); + TmpInst.addOperand(MCOperand::CreateImm(31)); + Inst = TmpInst; + break; + } + case PPC::SLWI: + case PPC::SLWIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo); TmpInst.addOperand(Inst.getOperand(0)); TmpInst.addOperand(Inst.getOperand(1)); TmpInst.addOperand(MCOperand::CreateImm(N)); @@ -484,10 +557,11 @@ ProcessInstruction(MCInst &Inst, Inst = TmpInst; break; } - case PPC::SRWI: { + case PPC::SRWI: + case PPC::SRWIo: { MCInst TmpInst; int64_t N = Inst.getOperand(2).getImm(); - TmpInst.setOpcode(PPC::RLWINM); + TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo); TmpInst.addOperand(Inst.getOperand(0)); TmpInst.addOperand(Inst.getOperand(1)); TmpInst.addOperand(MCOperand::CreateImm(32 - N)); @@ -496,10 +570,90 @@ ProcessInstruction(MCInst &Inst, Inst = TmpInst; break; } - case PPC::SLDI: { + case PPC::CLRRWI: + case PPC::CLRRWIo: { MCInst TmpInst; int64_t N = Inst.getOperand(2).getImm(); - TmpInst.setOpcode(PPC::RLDICR); + TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(0)); + TmpInst.addOperand(MCOperand::CreateImm(0)); + TmpInst.addOperand(MCOperand::CreateImm(31 - N)); + Inst = TmpInst; + break; + } + case PPC::CLRLSLWI: + case PPC::CLRLSLWIo: { + MCInst TmpInst; + int64_t B = Inst.getOperand(2).getImm(); + int64_t N = Inst.getOperand(3).getImm(); + TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(N)); + TmpInst.addOperand(MCOperand::CreateImm(B - N)); + TmpInst.addOperand(MCOperand::CreateImm(31 - N)); + Inst = TmpInst; + break; + } + case PPC::EXTLDI: + case PPC::EXTLDIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + int64_t B = Inst.getOperand(3).getImm(); + TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(B)); + TmpInst.addOperand(MCOperand::CreateImm(N - 1)); + Inst = TmpInst; + break; + } + case PPC::EXTRDI: + case PPC::EXTRDIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + int64_t B = Inst.getOperand(3).getImm(); + TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(B + N)); + TmpInst.addOperand(MCOperand::CreateImm(64 - N)); + Inst = TmpInst; + break; + } + case PPC::INSRDI: + case PPC::INSRDIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + int64_t B = Inst.getOperand(3).getImm(); + TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N))); + TmpInst.addOperand(MCOperand::CreateImm(B)); + Inst = TmpInst; + break; + } + case PPC::ROTRDI: + case PPC::ROTRDIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(64 - N)); + TmpInst.addOperand(MCOperand::CreateImm(0)); + Inst = TmpInst; + break; + } + case PPC::SLDI: + case PPC::SLDIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo); TmpInst.addOperand(Inst.getOperand(0)); TmpInst.addOperand(Inst.getOperand(1)); TmpInst.addOperand(MCOperand::CreateImm(N)); @@ -507,10 +661,11 @@ ProcessInstruction(MCInst &Inst, Inst = TmpInst; break; } - case PPC::SRDI: { + case PPC::SRDI: + case PPC::SRDIo: { MCInst TmpInst; int64_t N = Inst.getOperand(2).getImm(); - TmpInst.setOpcode(PPC::RLDICL); + TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo); TmpInst.addOperand(Inst.getOperand(0)); TmpInst.addOperand(Inst.getOperand(1)); TmpInst.addOperand(MCOperand::CreateImm(64 - N)); @@ -518,6 +673,31 @@ ProcessInstruction(MCInst &Inst, Inst = TmpInst; break; } + case PPC::CLRRDI: + case PPC::CLRRDIo: { + MCInst TmpInst; + int64_t N = Inst.getOperand(2).getImm(); + TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(0)); + TmpInst.addOperand(MCOperand::CreateImm(63 - N)); + Inst = TmpInst; + break; + } + case PPC::CLRLSLDI: + case PPC::CLRLSLDIo: { + MCInst TmpInst; + int64_t B = Inst.getOperand(2).getImm(); + int64_t N = Inst.getOperand(3).getImm(); + TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::CreateImm(N)); + TmpInst.addOperand(MCOperand::CreateImm(B - N)); + Inst = TmpInst; + break; + } } } diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 5b99a66..a9cfd5e 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -2290,14 +2290,89 @@ def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; +def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", + (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; +def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", + (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; +def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", + (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; +def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", + (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; +def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", + (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; +def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", + (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; +def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", + (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; +def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", + (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; +def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", + (ins gprc:$rA, gprc:$rS, u5imm:$n)>; +def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", + (ins gprc:$rA, gprc:$rS, u5imm:$n)>; def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", (ins gprc:$rA, gprc:$rS, u5imm:$n)>; +def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n", + (ins gprc:$rA, gprc:$rS, u5imm:$n)>; def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", (ins gprc:$rA, gprc:$rS, u5imm:$n)>; +def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n", + (ins gprc:$rA, gprc:$rS, u5imm:$n)>; +def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", + (ins gprc:$rA, gprc:$rS, u5imm:$n)>; +def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", + (ins gprc:$rA, gprc:$rS, u5imm:$n)>; +def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", + (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; +def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", + (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; + +def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; +def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; +def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; +def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; +def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; +def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; + +def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; +def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; +def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; +def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; +def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; +def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; +def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; +def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; +def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; +def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; +def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; +def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", + (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; +def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", + (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; +def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", + (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; + +def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; +def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; +def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; +def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; +def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; +def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; // These generic branch instruction forms are used for the assembler parser only. // Defs and Uses are conservative, since we don't know the BO value. diff --git a/test/MC/PowerPC/ppc64-encoding-ext.s b/test/MC/PowerPC/ppc64-encoding-ext.s index a194d1a..9f1d1c8 100644 --- a/test/MC/PowerPC/ppc64-encoding-ext.s +++ b/test/MC/PowerPC/ppc64-encoding-ext.s @@ -1848,57 +1848,99 @@ # Rotate and shift mnemonics -# FIXME: extldi 2, 3, 4, 5 -# FIXME: extldi. 2, 3, 4, 5 -# FIXME: extrdi 2, 3, 4, 5 -# FIXME: extrdi. 2, 3, 4, 5 -# FIXME: insrdi 2, 3, 4, 5 -# FIXME: insrdi. 2, 3, 4, 5 -# FIXME: rotldi 2, 3, 4 -# FIXME: rotldi. 2, 3, 4 -# FIXME: rotrdi 2, 3, 4 -# FIXME: rotrdi. 2, 3, 4 -# FIXME: rotld 2, 3, 4 -# FIXME: rotld. 2, 3, 4 +# CHECK: rldicr 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc4] + extldi 2, 3, 4, 5 +# CHECK: rldicr. 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc5] + extldi. 2, 3, 4, 5 +# CHECK: rldicl 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x20] + extrdi 2, 3, 4, 5 +# CHECK: rldicl. 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x21] + extrdi. 2, 3, 4, 5 +# CHECK: rldimi 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4e] + insrdi 2, 3, 4, 5 +# CHECK: rldimi. 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4f] + insrdi. 2, 3, 4, 5 +# CHECK: rldicl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x00] + rotldi 2, 3, 4 +# CHECK: rldicl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x01] + rotldi. 2, 3, 4 +# CHECK: rldicl 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x02] + rotrdi 2, 3, 4 +# CHECK: rldicl. 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x03] + rotrdi. 2, 3, 4 +# CHECK: rldcl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x10] + rotld 2, 3, 4 +# CHECK: rldcl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x11] + rotld. 2, 3, 4 # CHECK: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4] sldi 2, 3, 4 -# FIXME: sldi. 2, 3, 4 +# CHECK: rldicr. 2, 3, 4, 59 # encoding: [0x78,0x62,0x26,0xe5] + sldi. 2, 3, 4 # CHECK: rldicl 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x02] srdi 2, 3, 4 -# FIXME: srdi. 2, 3, 4 -# FIXME: clrldi 2, 3, 4 -# FIXME: clrldi. 2, 3, 4 -# FIXME: clrrdi 2, 3, 4 -# FIXME: clrrdi. 2, 3, 4 -# FIXME: clrlsldi 2, 3, 4, 5 -# FIXME: clrlsldi. 2, 3, 4, 5 - -# FIXME: extlwi 2, 3, 4, 5 -# FIXME: extlwi. 2, 3, 4, 5 -# FIXME: extrwi 2, 3, 4, 5 -# FIXME: extrwi. 2, 3, 4, 5 -# FIXME: inslwi 2, 3, 4, 5 -# FIXME: inslwi. 2, 3, 4, 5 -# FIXME: insrwi 2, 3, 4, 5 -# FIXME: insrwi. 2, 3, 4, 5 -# FIXME: rotlwi 2, 3, 4 -# FIXME: rotlwi. 2, 3, 4 -# FIXME: rotrwi 2, 3, 4 -# FIXME: rotrwi. 2, 3, 4 -# FIXME: rotlw 2, 3, 4 -# FIXME: rotlw. 2, 3, 4 +# CHECK: rldicl. 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x03] + srdi. 2, 3, 4 +# CHECK: rldicl 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x00] + clrldi 2, 3, 4 +# CHECK: rldicl. 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x01] + clrldi. 2, 3, 4 +# CHECK: rldicr 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe4] + clrrdi 2, 3, 4 +# CHECK: rldicr. 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe5] + clrrdi. 2, 3, 4 +# CHECK: rldic 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x48] + clrlsldi 2, 3, 5, 4 +# CHECK: rldic. 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x49] + clrlsldi. 2, 3, 5, 4 + +# CHECK: rlwinm 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x06] + extlwi 2, 3, 4, 5 +# CHECK: rlwinm. 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x07] + extlwi. 2, 3, 4, 5 +# CHECK: rlwinm 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3e] + extrwi 2, 3, 4, 5 +# CHECK: rlwinm. 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3f] + extrwi. 2, 3, 4, 5 +# CHECK: rlwimi 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x50] + inslwi 2, 3, 4, 5 +# CHECK: rlwimi. 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x51] + inslwi. 2, 3, 4, 5 +# CHECK: rlwimi 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x50] + insrwi 2, 3, 4, 5 +# CHECK: rlwimi. 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x51] + insrwi. 2, 3, 4, 5 +# CHECK: rlwinm 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3e] + rotlwi 2, 3, 4 +# CHECK: rlwinm. 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3f] + rotlwi. 2, 3, 4 +# CHECK: rlwinm 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3e] + rotrwi 2, 3, 4 +# CHECK: rlwinm. 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3f] + rotrwi. 2, 3, 4 +# CHECK: rlwnm 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3e] + rotlw 2, 3, 4 +# CHECK: rlwnm. 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3f] + rotlw. 2, 3, 4 # CHECK: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36] slwi 2, 3, 4 -# FIXME: slwi. 2, 3, 4 +# CHECK: rlwinm. 2, 3, 4, 0, 27 # encoding: [0x54,0x62,0x20,0x37] + slwi. 2, 3, 4 # CHECK: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e] srwi 2, 3, 4 -# FIXME: srwi. 2, 3, 4 -# FIXME: clrlwi 2, 3, 4 -# FIXME: clrlwi. 2, 3, 4 -# FIXME: clrrwi 2, 3, 4 -# FIXME: clrrwi. 2, 3, 4 -# FIXME: clrlslwi 2, 3, 4, 5 -# FIXME: clrlslwi. 2, 3, 4, 5 +# CHECK: rlwinm. 2, 3, 28, 4, 31 # encoding: [0x54,0x62,0xe1,0x3f] + srwi. 2, 3, 4 +# CHECK: rlwinm 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3e] + clrlwi 2, 3, 4 +# CHECK: rlwinm. 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3f] + clrlwi. 2, 3, 4 +# CHECK: rlwinm 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x36] + clrrwi 2, 3, 4 +# CHECK: rlwinm. 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x37] + clrrwi. 2, 3, 4 +# CHECK: rlwinm 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x76] + clrlslwi 2, 3, 5, 4 +# CHECK: rlwinm. 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x77] + clrlslwi. 2, 3, 5, 4 # Move to/from special purpose register mnemonics |