diff options
| -rw-r--r-- | lib/Target/X86/X86SelectionDAGInfo.cpp | 24 | ||||
| -rw-r--r-- | test/CodeGen/Generic/2010-11-04-BigByval.ll | 11 |
2 files changed, 28 insertions, 7 deletions
diff --git a/lib/Target/X86/X86SelectionDAGInfo.cpp b/lib/Target/X86/X86SelectionDAGInfo.cpp index c59d407..0c5a0ac 100644 --- a/lib/Target/X86/X86SelectionDAGInfo.cpp +++ b/lib/Target/X86/X86SelectionDAGInfo.cpp @@ -187,19 +187,29 @@ X86SelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, if (!AlwaysInline && SizeVal > Subtarget->getMaxInlineSizeThreshold()) return SDValue(); - /// If not DWORD aligned, call the library. - if ((Align & 3) != 0) + /// If not DWORD aligned, it is more efficient to call the library. However + /// if calling the library is not allowed (AlwaysInline), then soldier on as + /// the code generated here is better than the long load-store sequence we + /// would otherwise get. + if (!AlwaysInline && (Align & 3) != 0) return SDValue(); // If to a segment-relative address space, use the default lowering. if (DstPtrInfo.getAddrSpace() >= 256 || SrcPtrInfo.getAddrSpace() >= 256) return SDValue(); - - // DWORD aligned - EVT AVT = MVT::i32; - if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned - AVT = MVT::i64; + + MVT AVT; + if (Align & 1) + AVT = MVT::i8; + else if (Align & 2) + AVT = MVT::i16; + else if (Align & 4) + // DWORD aligned + AVT = MVT::i32; + else + // QWORD aligned + AVT = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; unsigned UBytes = AVT.getSizeInBits() / 8; unsigned CountVal = SizeVal / UBytes; diff --git a/test/CodeGen/Generic/2010-11-04-BigByval.ll b/test/CodeGen/Generic/2010-11-04-BigByval.ll new file mode 100644 index 0000000..df2ca4c --- /dev/null +++ b/test/CodeGen/Generic/2010-11-04-BigByval.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s +; PR7170 + +%big = type [131072 x i8] + +declare void @foo(%big* byval align 1) + +define void @bar(%big* byval align 1 %x) { + call void @foo(%big* byval align 1 %x) + ret void +} |