diff options
| -rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 12 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/fp128.ll | 17 |
2 files changed, 23 insertions, 6 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 641ab6c..2260fe4 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -2160,12 +2160,12 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, return RetAddr; } -static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG) +static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) { SDLoc dl(Op); assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); - assert(Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS); + assert(opcode == ISD::FNEG || opcode == ISD::FABS); // Lower fneg/fabs on f64 to fneg/fabs on f32. // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd. @@ -2177,7 +2177,7 @@ static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG) SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, SrcReg64); - Hi32 = DAG.getNode(Op.getOpcode(), dl, MVT::f32, Hi32); + Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0); @@ -2280,7 +2280,7 @@ static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool is64Bit) { if (Op.getValueType() == MVT::f64) - return LowerF64Op(Op, DAG); + return LowerF64Op(Op, DAG, ISD::FNEG); if (Op.getValueType() == MVT::f128) return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1); return Op; @@ -2288,7 +2288,7 @@ static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG, static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { if (Op.getValueType() == MVT::f64) - return LowerF64Op(Op, DAG); + return LowerF64Op(Op, DAG, ISD::FABS); if (Op.getValueType() != MVT::f128) return Op; @@ -2304,7 +2304,7 @@ static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { if (isV9) Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); else - Hi64 = LowerF64Op(Op, DAG); + Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS); SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f128), 0); diff --git a/test/CodeGen/SPARC/fp128.ll b/test/CodeGen/SPARC/fp128.ll index 1538199..e3d3613 100644 --- a/test/CodeGen/SPARC/fp128.ll +++ b/test/CodeGen/SPARC/fp128.ll @@ -96,3 +96,20 @@ entry: "7": ; preds = %entry ret i32 1 } + + +; HARD-LABEL: f128_abs +; HARD: fabss + +; SOFT-LABEL: f128_abs +; SOFT: fabss + +define void @f128_abs(fp128* noalias sret %scalar.result, fp128* byval %a) { +entry: + %0 = load fp128* %a, align 8 + %1 = tail call fp128 @llvm.fabs.f128(fp128 %0) + store fp128 %1, fp128* %scalar.result, align 8 + ret void +} + +declare fp128 @llvm.fabs.f128(fp128) nounwind readonly |